Patents by Inventor Satoru Itakura

Satoru Itakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105681
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes placing a first semiconductor element on a wiring board, forming a first mask having an opening on the wiring board so that the first semiconductor element is positioned in the opening, putting a liquid first resin precursor into the opening of the first mask, curing the first resin precursor to obtain a first resin layer, and then removing the first mask.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 28, 2024
    Inventors: Satoru ITAKURA, Masayuki MIURA
  • Publication number: 20230282616
    Abstract: A semiconductor device includes: a wiring board having a surface; a chip stack disposed above the surface and including a first semiconductor chip; a second semiconductor chip disposed between the surface and the chip stack; a spacer disposed between the surface and the first semiconductor chip, the spacer surrounding the second semiconductor chip along the surface, and the spacer containing a material higher in thermal conductivity than silicon; and a sealing insulation layer covering the chip stack.
    Type: Application
    Filed: August 19, 2022
    Publication date: September 7, 2023
    Applicant: Kioxia Corporation
    Inventor: Satoru ITAKURA
  • Publication number: 20230282536
    Abstract: According to one embodiment, a semiconductor device includes a wiring substrate having a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface. A first electrode is on the first surface. A semiconductor element is on the wiring substrate and electrically connected to the first electrode. A resin layer covers the semiconductor element and the first surface from a first direction orthogonal to the first surface. A portion of the resin layer contacts the side surface of the wiring substrate from a second direction parallel to the first surface. The resin layer has an outside side surface that is substantially parallel to the first direction.
    Type: Application
    Filed: August 26, 2022
    Publication date: September 7, 2023
    Inventors: Kazushige Kawasaki, Satoru Itakura
  • Publication number: 20230268310
    Abstract: According to one embodiment, a semiconductor device includes: a circuit board; a first semiconductor chip mounted on a face of the circuit board; a resin film covering the first semiconductor chip; and a second semiconductor chip having a chip area larger than a chip area of the first semiconductor chip, the second semiconductor chip being stuck to an upper face of the resin film and mounted on the circuit board. The resin film entirely fits within an inner region of a bottom face of the second semiconductor chip when viewed in a stacking direction of the first and second semiconductor chips.
    Type: Application
    Filed: September 7, 2022
    Publication date: August 24, 2023
    Applicant: Kioxia Corporation
    Inventor: Satoru ITAKURA
  • Patent number: 8897051
    Abstract: A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: November 25, 2014
    Assignee: J-Devices Corporation
    Inventors: Satoru Itakura, Akio Katsumata, Akihiro Umeki, Yasushi Shiraishi, Junichiro Abe
  • Patent number: 8872350
    Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 28, 2014
    Assignee: J-Devices Corporation
    Inventors: Shigenori Sawachi, Osamu Yamagata, Hiroshi Inoue, Satoru Itakura, Tomoshige Chikai, Masahiko Hori, Akio Katsumata
  • Publication number: 20140104953
    Abstract: A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 17, 2014
    Applicant: J-DEVICES CORPORATION
    Inventors: Satoru ITAKURA, Akio Katsumata, Akihiro Umeki, Yasushi Shiraishi, Junichiro Abe
  • Publication number: 20130200523
    Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 8, 2013
    Inventors: Shigenori SAWACHI, Osamu Yamagata, Hiroshi Inoue, Satoru Itakura, Tomoshige Chikai, Masahiko Hori, Akio Katsumata
  • Publication number: 20130026650
    Abstract: A semiconductor device is made up of an organic substrate; through vias which penetrate the organic substrate in its thickness direction; external electrodes and internal electrodes provided to the front and back faces of the organic substrate and electrically connected to the through vias; a semiconductor element mounted on one main surface of the organic substrate via a bonding layer, with an element circuit surface thereof facing upward; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part of this metal thin film wiring layer being exposed on an external surface; metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer; and external electrodes formed on the metal thin film wiring layer.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Inventors: Osamu Yamagata, Akio Katsumata, Hiroshi Inoue, Shigenori Sawachi, Satoru Itakura, Yasuhiro Yamaji