Abstract: A diagnosis processing device is provided in which diagnosis is realizable by a simple arrangement. A diagnosis processing device (1) of the present invention includes: a learning pattern creating section (10a) for creating a learning pattern by sampling data from a learning image in which abnormality information indicating a substantive feature of abnormality of a target is pre-known; a learning processing section (12) for causing a neural network (17) to learn, by using learning patterns; a diagnostic pattern creating section (10b) for creating a diagnostic pattern by sampling data from a diagnostic image in which abnormality information is unknown; a determination processing section (18) for determining a substantive feature of the abnormality of the target indicated in the abnormality information in the diagnostic image, based on an output value outputted, in response to an input of the diagnostic pattern, from a learned neural network (17) which is a neural network subjected to learning.

Abstract: A diagnosis processing device is provided in which diagnosis is realizable by a simple arrangement. A diagnosis processing device (1) of the present invention includes: a learning pattern creating section (10a) for creating a learning pattern by sampling data from a learning image in which abnormality information indicating a substantive feature of abnormality of a target is pre-known; a learning processing section (12) for causing a neural network (17) to learn, by using learning patterns; a diagnostic pattern creating section (10b) for creating a diagnostic pattern by sampling data from a diagnostic image in which abnormality information is unknown; a determination processing section (18) for determining a substantive feature of the abnormality of the target indicated in the abnormality information in the diagnostic image, based on an output value outputted, in response to an input of the diagnostic pattern, from a learned neural network (17) which is a neural network subjected to learning.

Abstract: In the present flash memory a threshold voltage of a memory transistor to which data is written is detected and the detected value is used to set an initial value of a pulse voltage of a write pulse signal, and whenever the write pulse signal is applied, the pulse voltage is increased by a step voltage. The memory transistor's drain current and the threshold voltage's variation can be smaller than when a fixed pulse voltage is applied, as conventional.

Abstract: In the present flash memory a threshold voltage of a memory transistor to which data is written is detected and the detected value is used to set an initial value of a pulse voltage of a write pulse signal, and whenever the write pulse signal is applied, the pulse voltage is increased by a step voltage. The memory transistor's drain current and the threshold voltage's variation can be smaller than when a fixed pulse voltage is applied, as conventional.

Abstract: A layout apparatus allowing efficient layout editing includes a circuit for selecting a logic gate forming a semiconductor integrated circuit, and a circuit for generating, on the basis of a logic gate, a layout cell of transistors forming the logic gate based on the size information on the transistors forming the logic gate and the type of the logic gate.

Abstract: A circuit connection information generating device for generating circuit connection information which correctly reflects circuit connection information provided from a circuit drawing and which contains parasitic elements is disclosed.

Abstract: An internal logic gate portion (3) is provided in the central portion of a semiconductor chip (1), input/output buffers (4) are provided to surround the internal logic gate portion (3), and bonding pads (2) are provided in the peripheral portions of the semiconductor chip (1) corresponding to input/output buffer cells (5) in the input/output buffer. Each of the input/output buffer cells (5) comprises an output P-MOS portion (6), an output N-MOS portion (7), an input/logic P-MOS portion (8) and an input/logic N-MOS portion (9), which are respectively arranged in a single line in the direction from the bonding pads (2) to the internal logic gate portion (3). In the above described structure, the size of each of the input/output buffer cells (5) in the pad arranging direction of the bonding pads (2) is decreased, so that the number of input/output pins can be increased according to the decreased use of space in the pad arranging direction required by each input/output buffer cell (5).

Abstract: In a read only memory, a current type sense amplifiers connected to an array of memory cells includes a charge supply circuit for maintaining an output voltage of an inverter. At the time of first accessing, when the input node is brought to temporarlly increased potential level by the delay at the inverter, the node is maintained at a predetermined potential level by the operation of the circuit. In this manner, the time until the node is changed to the high level at the time of second accessing may be shortened. That is, the operating speed of the sense amplifier is increased.

Abstract: A semiconductor integrated circuit device of a multi-layer type having a plurality of semiconductor chips. The device comprises a plurality of semiconductor chips each having a plurality of electrode pads, a plurality of wiring films which are arranged in correspondence with the semiconductor chips and on which the corresponding semiconductor chips are mounted, a plurality of first terminals provided in each of the wiring films and respectively connected to the plurality of electrode pads of the semiconductor chip corresponding to the wiring film, and a plurality of second terminals disposed beyond the first terminals of each wiring film and electrically connected to the respective first terminals.

Abstract: A semiconductor integrated circuit includes cascaded asynchronous sequential logic circuits. Scanning shift registers are provided between the asynchronous sequential circuits to permit test data to be applied to the inputs of the circuits and to latch and shift out output data provided by the circuits in response to the test data. Additional gating circuitry is provided between the scanning shift registers and the inputs of the asynchronous sequential circuits to prevent new data latched into the scanning shift register from causing the asynchronous sequential circuit connected to the scanning shift register output from changing state during testing. This same additional circuitry may be used to provide pulses of controlled width and/or timing to asynchronous sequential circuit inputs in response to externally generated gating control signals.

Abstract: A semiconductor integrated circuit device for transmitting data between a plurality of circuit blocks at least one thereof including a sequential circuit and enabling the circuit blocks to test in a scan testing type which has a plurality of scan registers provided between the plurality of circuit blocks corresponding to the number of bits of data to be transmitted for outputting the output data of the previous stage circuit block as it is at ordinary operating time and for holding and outputting the output data of the previous circuit block or test data for scan test synchronously with an external clock at testing time so that the circuits are connected by a shift register pass in such a manner that the entirety has one shaft register function, and a latch circuit provided at its data input terminal to the data output terminal of the corresponding scan register for outputtting the output data of the corresponding scan register as it is to the circuit block of next stage at ordinary operation time and holding

Abstract: A test circuit of a semiconductor integrated circuit apparatus comprising a latch circuit connected to an output terminal of a scan register for holding output data of the scan register stored before scanning in a scan mode during the test operation.

Abstract: A semiconductor logic integrated circuit device comprising a signal selection means and a storing means, which is capable of adjusting the logic levels of an output signal therefrom. With such a circuit device, the signal selection means and the storing means are controlled in normal operation mode so that a parallel input signal is allowed to be output as a parallel output signal from output terminals of the circuit device after subjecting the parallel input signal to logical signal processing. On the other hand, the signal selection means and the storing means are controlled in a testing opertion mode so that the parallel input signal are output in serial mode from a serial signal output terminal of the circuit device, and a serial input signal to the signal selection means is allowed to be stored in the storing means to adjust the logic levels of the output signal from the circuit device at desired levels voluntarily.

Abstract: A semiconductor integrated circuit device includes a plurality of latch circuits which are provided between adjacent circuit blocks. Each latch circuit functions to transfer output data from a preceding circuit block directly to a subsequent circuit block during a normal operation of the circuit device, to hold the output data until a scanning of associated scan register and supply them to the subsequent circuit block in a scan mode of a test operation and to hole the output data while outputting them in synchronism with an external clock in a test mode of the test operation.