Abstract: An electrostatic breakdown protection circuit and a capacitance sensor device are provided. An electrostatic breakdown protection circuit included in an electronic device including an external terminal and an internal circuit connected to the external terminal includes: a first series diode group in which n diodes including a first diode having an anode connected to the external terminal and a second diode having a cathode applied with a power supply voltage are connected in series; and a second series diode group in which n diodes including a third diode having a cathode connected to the external terminal and a fourth diode having an anode applied with a ground voltage are connected in series.

Abstract: The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground line is supplied to a second ground line. A virtual source line and a virtual ground line are respectively connected to the second source line and the first ground line by switches in an operation mode and float thereby in the standby mode. Substrates of MOS transistors are respectively connected to the second source line and the first ground line by switches in the operation mode and connected to the first source line and the second ground line thereby in the standby mode. A gate circuit transmits an output signal of a data non-holding circuit to a data holding circuit in the operation mode and fixes an input signal of the data holding circuit in the standby mode.

Abstract: The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground line is supplied to a second ground line. A virtual source line and a virtual ground line are respectively connected to the second source line and the first ground line by switches in an operation mode and float thereby in the standby mode. Substrates of MOS transistors are respectively connected to the second source line and the first ground line by switches in the operation mode and connected to the first source line and the second ground line thereby in the standby mode. A gate circuit transmits an output signal of a data non-holding circuit to a data holding circuit in the operation mode and fixes an input signal of the data holding circuit in the standby mode.

Abstract: In a power circuit, first and second voltage-dividing capacitors are connected in series between first and second power terminals in even cycles. On the other hand, the first and second voltage-dividing capacitors are connected in series between the second and first power terminals in odd cycles, which occur alternately with the even cycles.

Abstract: A reference voltage for obtaining a desired output voltage value, and an output voltage are inputted to an operational amplifier. A PMOS transistor whose on/off operation is controlled by the operational amplifier, outputs an internal node voltage therefrom. A switch control circuit outputs a signal constant in duty ratio, for activating CHG switches and DCHG switches respectively. A voltage dividing capacitor and an output capacitor respectively repeat charging and discharging based on a switching pulse constant in duty ratio. Accordingly, a stable output voltage obtained by series/parallel connection switching operations of two capacitors results in ½ of the internal node voltage.

Abstract: In a power circuit, first and second voltage-dividing capacitors are connected in series between first and second power terminals in even cycles. On the other hand, the firs and second voltage-dividing capacitors are connected in series between the second and first power terminals in odd cycles, which occur alternately with the even cycles.

Abstract: A semiconductor integrated circuit related to the present invention comprises a logic circuit, and a mode-switching circuit. The logic circuit has a multiplicity of logic elements, which are driven by a driving voltage applied from a dummy power supply line. The mode-switching circuit, during an active mode, supplies to the dummy power supply line a first electric potential for driving a logic element, and, during a sleep mode, supplies to the dummy power supply line a second electric potential, which is higher than zero volts, and lower than a first electric potential. In a first preferred embodiment, a second electric potential is set to a value such that it is possible to reduce logic circuit OFF leakage current during a sleep mode, and to shorten the time for transitioning from a sleep mode to an active mode.

Abstract: A reference voltage for obtaining a desired output voltage value, and an output voltage are inputted to an operational amplifier. A PMOS transistor whose on/off operation is controlled by the operational amplifier, outputs an internal node voltage therefrom. A switch control circuit outputs a signal constant in duty ratio, for activating CHG switches and DCHG switches respectively. A voltage dividing capacitor and an output capacitor respectively repeat charging and discharging based on a switching pulse constant in duty ratio. Accordingly, a stable output voltage obtained by series/parallel connection switching operations of two capacitors results in ½ of the internal node voltage.

Abstract: Complementary read signals Bi, /Bi applied to bit line pair 1i, 2i are compared with complementary address signals Ai, /Ai in a comparison unit 10i. The result of the comparison is output to output lines 15i, 16i as complementary detection signals. The detection signals on the output lines 15i, 16i are applied to the amplifier unit 20i which starts amplifying operation, when the level “H” is applied to terminals E. An enable signal EN from outside of the circuit is applied to the first stage amplifier unit 201 of the first group and the first stage amplifier unit 20n+1 of the second group, of which output signals are applied to the terminals E of the succeeding amplifier units 202 to 20n, and 20n+2 to 202n. With this structure, the amount of electric consumption can be reduced with scarcely increasing time required for operation.

Abstract: A multiple-bit comparator compares the individual bits of a first multiple-bit signal with the corresponding bits of a second multiple-bit signal. An output control circuit in the multiple-bit comparator detects, from transitions in the second signal, whether the second signal is valid or invalid, and holds an output signal at a fixed logic level when the second signal is invalid. When the second signal is valid, the output signal is controlled according to the combined results of the individual bit comparisons. The individual bit comparison results are preferably combined by wired-OR logic.