Patents by Inventor Satoru Masaki

Satoru Masaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959324
    Abstract: A control system includes a contact sensor configured to detect contact between an operation body and a door handle, a force sensor configured to detect a force applied by the operation body to the door handle, and a controller configured to control opening or closing of a door when the contact is detected by the contact sensor and the force is detected by the force sensor.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: April 16, 2024
    Assignee: ALPS ALPINE CO., LTD.
    Inventors: Masahiro Takata, Takeshi Masaki, Kazuhito Oshita, Satoru Takizawa
  • Patent number: 8698290
    Abstract: An LED lamp (A1) includes a plurality of LEDs (2), a retainer (1) on which the light LEDs (2) are mounted, and a wiring pattern formed on the retainer (1) and electrically connected to the LEDs (2). The retainer (1) includes a plurality of substrates (11, 12, 15). Of the plurality of substrates (11, 12, 15), two adjacent substrates (11, 12) are connected to each other by a pair of bendable connection members (32a, 32b). The two substrates (11, 12) are arranged in such a manner that their normal line directions differ from each other.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: April 15, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuya Masumoto, Satoru Masaki, Hironobu Kaneko
  • Publication number: 20110204393
    Abstract: An LED lamp (A1) includes a plurality of LEDs (2), a retainer (1) on which the light LEDs (2) are mounted, and a wiring pattern formed on the retainer (1) and electrically connected to the LEDs (2). The retainer (1) includes a plurality of substrates (11, 12, 15). Of the plurality of substrates (11, 12, 15), two adjacent substrates (11, 12) are connected to each other by a pair of bendable connection members (32a, 32b). The two substrates (11, 12) are arranged in such a manner that their normal line directions differ from each other.
    Type: Application
    Filed: November 6, 2009
    Publication date: August 25, 2011
    Applicant: ROHM CO., LTD.
    Inventors: Tatsuya Masumoto, Satoru Masaki, Hironobu Kaneko
  • Patent number: 5680064
    Abstract: A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: October 21, 1997
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Satoru Masaki, Akinori Yamamoto, Fusao Seki, Fumitaka Asami, Kazuo Ohno, Masao Imai, Shinya Udo
  • Patent number: 5379175
    Abstract: A semiconductor integrated circuit device includes an internal logic circuit which is reset in response to a reset signal, and an abnormal voltage detection circuit, operatively connected to said internal logic circuit and an external terminal, for generating the reset signal when an abnormal voltage is detected at the external terminal.
    Type: Grant
    Filed: May 15, 1992
    Date of Patent: January 3, 1995
    Assignee: Fujitsu Limited
    Inventor: Satoru Masaki
  • Patent number: 4513400
    Abstract: A circuit for reading out address data applied to a memory in a one-chip microcomputer which does not have any address terminals but has input/output terminals. The circuit comprises a program counter for specifying reading out addresses of the memory. Transfer gates and a shift register are also provided. The transfer gates transfer the contents of the program counter to the shift register when an address output enable signal is applied to the transfer gates. The contents stored in the shift register are read out to an address output terminal connected to the shift register.
    Type: Grant
    Filed: June 22, 1982
    Date of Patent: April 23, 1985
    Assignee: Fujitsu Limited
    Inventor: Satoru Masaki