Abstract: An organic light-emitting device includes, in sequence, a first electrode, a first light-emitting layer, a charge transport layer, a charge generation portion, a second light-emitting layer, and a second electrode. The charge transport layer contains a fused polycyclic hydrocarbon compound.

Abstract: A cylindrical battery according to one embodiment comprises: an electrode assembly obtained by wrapping a positive electrode and a negative electrode around a separator; an electrolyte; a bottomed cylindrical outer can that houses the electrode assembly and the electrolyte; a sealing body that plugs the opening of the outer can; and an annular gasket that is inserted between the outer can and the sealing body. The sealing body is anchored by being crimped to an open end of the outer can via the gasket. The gasket has a projection formed on the outer peripheral surface thereof, the projection protruding outside radially and the projection is in contact with the inner peripheral surface of the open end of the outer casing.

Abstract: The secondary cell—includes an exterior can, a sealing body closing one end of the exterior can, an electrode group disposed inside the exterior can, and an insulating plate disposed between the sealing body and the electrode group. In the electrode group, a positive electrode and a negative electrode are wound in a spiral shape with a separator interposed between. The insulating plate is shaped as a disc having a lead hole penetrated by a positive electrode lead drawn out from the electrode group, and a center hole penetrating the center part of the insulating plate. The outer edge of the lead hole includes a curve part positioned along an arc that is concentric with respect to the outer circumference of the insulating plate as seen in plan view, and linear parts-positioned along a chord linking the two ends of the arc.

Abstract: A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.

Abstract: A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.

Abstract: A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.

Abstract: A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.

Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.

Abstract: The invention provides a method for removing bacteria From antibody-containing milk that has been expressed from a bovid animal producing antibodies by sensitization with one or more antigens selected from among pathogens and their metabolic products, characterized in that defatting treatment is followed by filtration using a microfilter comprising a support and a filter membrane formed from ceramic fine particles, having filtration pores and a thickness between 40 to 150 &mgr;m.

Abstract: A method for the fabrication of a cap layer on a top electrode layer of a ferroelectric capacitor includes the steps of depositing an amorphous layer, usually made of Sr(x)Ru(y)O3, on the top electrode and then annealing the amorphous layer in two stages in order convert the amorphous layer into the cap layer. The first anneal is performed at 500° C. to 700° C. in a non-oxidizing atmosphere, such as nitrogen, and converts the amorphous layer into a crystallized layer of Sr(x)Ru(y)O3. The second anneal is performed at 300° C. to 500° C. in an oxidizing atmosphere, such as oxygen, and converts the crystallized layer into the cap layer. The method is applied to the formation of a ferroelectric capacitor element of an integrated semiconductor device.

Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.

Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.

Abstract: A method for the fabrication of a cap layer on a top electrode layer of a ferroelectric capacitor includes the steps of depositing an amorphous layer, usually made of Sr(x)Ru(y)O3, on the top electrode and then annealing the amorphous layer in two stages in order convert the amorphous layer into the cap layer. The first anneal is performed at 500° C. to 700° C. in a non-oxidizing atmosphere, such as nitrogen, and converts the amorphous layer into a crystallized layer of Sr(x)Ru(y)O3. The second anneal is performed at 300° C. to 500° C. in an oxidizing atmosphere, such as oxygen, and converts the crystallized layer into the cap layer. The method is applied to the formation of a ferroelectric capacitor element of an integrated semiconductor device.

Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.

Abstract: There is provided an RF sputtering film forming method of forming a compound film having a stable composition by use of stable plasma with a broad process window to thus facilitate composition control of the compound film. In the RF sputtering film forming method, an alternating voltage or alternating current is applied to a part or all of walls positioned on the outside of a space formed between a wafer and a target, or an electron temperature in the plasma is reduced by oscillating the RF power in a pulse fashion, or a sputtering gas is composed of at least one kind of gases of helium, neon, xenon, and krypton, or a minus voltage is applied to a part or all of the walls positioned on the outside of the space formed between the wafer and the target.

Abstract: A carbon-containing film, which is made of a carbon-containing material, is adhered to the inner wall of a chamber. A semiconductor substrate is arranged in the chamber whose inner wall has the carbon-containing film adhered thereto. A plasma of a process gas which contains a rare gas is generated in the chamber, and such an electric field as to cause ions contained in the plasma to be attracted to a surface of the semiconductor substrate is applied in order to etch a part of the surface layer of the semiconductor substrate. During the etching, a film which contains a constituent or constituents of an etched film adheres to the surface of the carbon-containing film. The carbon-containing film prevents the peeling off of such an adhering film from the inner wall of the chamber, thereby reducing the generation of particles.

Abstract: Ashing process of a resist pattern used in a semiconductor device manufacturing method is conducted by exposing the resist, the wirings, and their peripheral regions to a first atmosphere which includes a first product obtained by plasmanizing a gas containing water at a rate of more than 30 flow rate %, and placing the resist in a second atmosphere which includes a second product obtained by plasmanizing an oxygen mixed gas which contains an oxygen gas as a principal component before or after or before and after the exposing step.

Abstract: In a method of manufacturing a semiconductor device, a first film essentially consisting of silicon is deposited on the surface of a semiconductor substrate. A second film essentially consisting of material having a proper etching selection ratio relative to tungsten is deposited on the first film. A third film essentially consisting of tungsten is deposited on the second film. A resist pattern is formed on the third film. The third film is etched and patterned to the surface of the second film, by using the resist pattern as a mask. The second film is etched to have the same shape as the third film. The first film is etched to have the same shape as the third film. After the step of patterning the third film and before the step of patterning the first film, the resist pattern is heated to a temperature of 80.degree. C. or higher, the semiconductor substrate is exposed in atmospheric air, and the resist pattern is removed.

Abstract: A method for performing plasma downstream processing by generating plasma of an oxygen-containing gas with a microwave in a space having a thickness of 1/10, or less, of a wavelength .lambda. of the microwave, deriving the generated plasma of the oxygen containing gas from such space through an opening formed around the central portion of such plasma generating space through a gap having a loop-shaped cross section in a plane parallel to the space and folded cross section in a plane including a central portion normal to such space; and irradiating the generated plasma of the oxygen containing gas derived from the plasma generating space to an object to be processed.

Abstract: A method of manufacturing a semiconductor device including the steps of: forming an insulating film on a silicon substrate; forming a resist pattern on the insulating film; etching the insulating film by using the resist pattern as an etching mask to expose a surface of the silicon substrate; and ashing the resist pattern and etching a surface layer at the exposed surface of the silicon substrate at the same time. The ashing/etching step may be performed first at a high temperature at or above 40.degree. C. and then at a lower temperature.