Patents by Inventor Satoru Mitani

Satoru Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9390797
    Abstract: A method of driving a variable resistance element comprises: before a first write step is performed, applying an initial voltage pulse of a first polarity to change a resistance value of a metal oxide layer from a resistance value corresponding to an initial state of the metal oxide layer to another resistance value; wherein when the resistance value corresponding to the initial state is R0, the resistance value corresponding to a write state is RL, the resistance value corresponding to an erase state is RH, another resistance value is R2, a maximum value of the current flowing when the initial voltage pulse is applied is IbRL, a maximum value of the current flowing when the write voltage pulse is applied is IRL, and a maximum value of the current flowing when the erase voltage pulse is applied is IRH, R0>RH>R2?RL, and |IRL|>|IbRL| are satisfied.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shunsaku Muraoka, Satoru Mitani, Takeshi Takagi, Koji Katayama
  • Patent number: 9153319
    Abstract: A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR<PWHR.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: October 6, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shunsaku Muraoka, Satoru Mitani, Takeshi Takagi
  • Patent number: 9111610
    Abstract: A method of driving a nonvolatile memory element including a variable resistance element having a state reversibly changing between low and high resistance states by an applied electrical signal and a transistor serially connected to the variable resistance element. The method including: setting the variable resistance element to the low resistance state by applying a first gate voltage to a gate of the transistor and applying a first write voltage negative with respect to a first electrode; and changing a resistance value of the transistor obtained in a low-resistance write operation, when a value of current passing through the variable resistance element in the setting of the low resistance state or a resistance value of the nonvolatile memory element in the case where the variable resistance element is in the low resistance state is outside a predetermined range.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: August 18, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koji Katayama, Satoru Mitani, Shunsaku Muraoka, Zhiqiang Wei, Takeshi Takagi
  • Patent number: 9082479
    Abstract: A nonvolatile memory device includes: a first electrode; a second electrode; and a variable resistance layer which includes: a first oxide layer including a first metal oxide; a second oxide layer located between and in contact with the first oxide layer and a second electrode including a second metal oxide and having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first oxide layer; and a local region located in the first oxide layer and the second oxide layer, having contact with the second electrode and no contact with the first electrode, and having a degree of oxygen deficiency higher than the degree of oxygen deficiency of the second oxide layer and different from the degree of oxygen deficiency of the first oxide layer.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: July 14, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Zhiqiang Wei, Takeshi Takagi, Satoru Mitani, Shunsaku Muraoka, Koji Katayama
  • Patent number: 9006698
    Abstract: A variable resistance element including: a first electrode; a second electrode; and a variable resistance layer having a resistance value which reversibly changes according to electrical signals applied, wherein the variable resistance layer includes a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first oxygen-deficient transition metal oxide, the second electrode has a single needle-shaped part at an interface with the second variable resistance layer, and the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers the single needle-shaped part.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: April 14, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Zhiqiang Wei, Takeshi Takagi, Satoru Mitani, Yoshio Kawashima, Ichirou Takahashi
  • Patent number: 8942025
    Abstract: A variable resistance nonvolatile memory element writing method according to the present disclosure includes: (a) changing a variable resistance layer to a low resistance state by applying, to a second electrode, a first voltage which is negative with respect to a first electrode; and (b) changing the variable resistance layer to a high resistance state. Step (b) includes: (i) applying, to the second electrode, a second voltage which is positive with respect to the first electrode; and (ii) changing the variable resistance layer to the high resistance state by applying, to the second electrode, a third voltage, which is negative with respect to the first electrode and is smaller than the absolute value of a threshold voltage for changing the variable resistance layer from the high resistance state to the low resistance state, after the positive second voltage is applied in step (i).
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: January 27, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Koji Katayama, Satoru Mitani, Takeshi Takagi
  • Patent number: 8830730
    Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate, (ii) a variable resistance element having: lower and upper electrodes; and a variable resistance layer whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes, and (iii) a MOS transistor formed on the substrate, wherein the variable resistance layer includes: oxygen-deficient transition metal oxide layers having compositions MOx and MOy (where x<y) and in contact with the electrodes respectively, a diffusion layer region is connected with the lower electrode to form a memory cell, the region serving as a drain upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: September 9, 2014
    Assignee: Panasonic Corporation
    Inventors: Shunsaku Muraoka, Yoshihiko Kanzawa, Satoru Mitani, Koji Katayama, Kazuhiko Shimakawa, Satoru Fujii, Takeshi Takagi
  • Publication number: 20140126268
    Abstract: A method of driving a nonvolatile memory element including a variable resistance element having a state reversibly changing between low and high resistance states by an applied electrical signal and a transistor serially connected to the variable resistance element. The method including: setting the variable resistance element to the low resistance state by applying a first gate voltage to a gate of the transistor and applying a first write voltage negative with respect to a first electrode; and changing a resistance value of the transistor obtained in a low-resistance write operation, when a value of current passing through the variable resistance element in the setting of the low resistance state or a resistance value of the nonvolatile memory element in the case where the variable resistance element is in the low resistance state is outside a predetermined range.
    Type: Application
    Filed: April 17, 2013
    Publication date: May 8, 2014
    Applicant: Panasonic Corporation
    Inventors: Koji Katayama, Satoru Mitani, Shunsaku Muraoka, Zhiqiang Wei, Takeshi Takagi
  • Publication number: 20140050014
    Abstract: A method of driving a variable resistance element comprises: before a first write step is performed, applying an initial voltage pulse of a first polarity to change a resistance value of a metal oxide layer from a resistance value corresponding to an initial state of the metal oxide layer to another resistance value; wherein when the resistance value corresponding to the initial state is R0, the resistance value corresponding to a write state is RL, the resistance value corresponding to an erase state is RH, another resistance value is R2, a maximum value of the current flowing when the initial voltage pulse is applied is IbRL, a maximum value of the current flowing when the write voltage pulse is applied is IRL, and a maximum value of the current flowing when the erase voltage pulse is applied is IRH, R0>RH>R2?RL, and |IRL|>|IbRL| are satisfied.
    Type: Application
    Filed: December 11, 2012
    Publication date: February 20, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Shunsaku Muraoka, Satoru Mitani, Takeshi Takagi, Koji Katayama
  • Publication number: 20140029330
    Abstract: A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR<PWHR.
    Type: Application
    Filed: March 13, 2012
    Publication date: January 30, 2014
    Inventors: Shunsaku Muraoka, Satoru Mitani, Takeshi Takagi
  • Publication number: 20140008599
    Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate, (ii) a variable resistance element having: lower and upper electrodes; and a variable resistance layer whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes, and (iii) a MOS transistor formed on the substrate, wherein the variable resistance layer includes: oxygen-deficient transition metal oxide layers having compositions MOx and MOy (where x<y) and in contact with the electrodes respectively, a diffusion layer region is connected with the lower electrode to form a memory cell, the region serving as a drain upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer.
    Type: Application
    Filed: September 6, 2013
    Publication date: January 9, 2014
    Applicant: Panasonic Corporation
    Inventors: Shunsaku MURAOKA, Yoshihiko KANZAWA, Satoru MITANI, Koji KATAYAMA, Kazuhiko SHIMAKAWA, Satoru FUJII, Takeshi TAKAGI
  • Patent number: 8553444
    Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOX and MOy (where x<y) and in contact with the electrodes (309a, 309c) respectively, and a diffusion layer region (302b) is connected with the lower electrode (309a) to form a memory cell (300), the region (302b) serving as a drain of the transistor (317) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer (309b).
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Shunsaku Muraoka, Yoshihiko Kanzawa, Satoru Mitani, Koji Katayama, Kazuhiko Shimakawa, Satoru Fujii, Takeshi Takagi
  • Patent number: 8553446
    Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9?x?1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8<y<2.0) are stacked together.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: October 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Satoru Mitani, Yoshihiko Kanzawa, Koji Katayama, Takeshi Takagi
  • Publication number: 20130250658
    Abstract: A nonvolatile memory device includes: a first electrode; a second electrode; and a variable resistance layer which includes: a first oxide layer including a first metal oxide; a second oxide layer located between and in contact with the first oxide layer and a second electrode including a second metal oxide and having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first oxide layer; and a local region located in the first oxide layer and the second oxide layer, having contact with the second electrode and no contact with the first electrode, and having a degree of oxygen deficiency higher than the degree of oxygen deficiency of the second oxide layer and different from the degree of oxygen deficiency of the first oxide layer.
    Type: Application
    Filed: October 3, 2012
    Publication date: September 26, 2013
    Applicant: Panasonic Corporation
    Inventors: Zhiqiang Wei, Takeshi Takagi, Satoru Mitani, Shunsaku Muraoka, Koji Katayama
  • Publication number: 20130242642
    Abstract: A variable resistance nonvolatile memory element writing method according to the present disclosure includes: (a) changing a variable resistance layer to a low resistance state by applying, to a second electrode, a first voltage which is negative with respect to a first electrode; and (b) changing the variable resistance layer to a high resistance state. Step (b) includes: (i) applying, to the second electrode, a second voltage which is positive with respect to the first electrode; and (ii) changing the variable resistance layer to the high resistance state by applying, to the second electrode, a third voltage, which is negative with respect to the first electrode and is smaller than the absolute value of a threshold voltage for changing the variable resistance layer from the high resistance state to the low resistance state, after the positive second voltage is applied in step (i).
    Type: Application
    Filed: August 9, 2012
    Publication date: September 19, 2013
    Inventors: Koji Katayama, Satoru Mitani, Takeshi Takagi
  • Patent number: 8472238
    Abstract: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt<V2 and V1<V2, and the lower electrode (309a) is connected with the N-type diffusion layer region (302b), the electrical signals being applied between the lower and upper electrodes (309a, 309c).
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazuhiko Shimakawa, Yoshihiko Kanzawa, Satoru Mitani, Shunsaku Muraoka
  • Patent number: 8445319
    Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshihiko Kanzawa, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhiko Shimakawa
  • Patent number: 8445885
    Abstract: A nonvolatile memory element includes first and second electrodes, and a resistance variable layer disposed therebetween. At least one of the first and second electrodes includes a platinum-containing layer. The resistance variable layer includes a first oxygen-deficient transition metal oxide layer which is not physically in contact with the platinum-containing layer and a second oxygen-deficient transition metal oxide layer which is disposed between the first oxygen-deficient transition metal oxide layer and the platinum-containing layer and is physically in contact with the platinum-containing layer. When oxygen-deficient transition metal oxides included in the first and second oxygen-deficient transition metal oxide layers are expressed as MOx, and MOy, respectively, x<y is satisfied. The platinum-containing layer has a thickness which is not less than 1 nm and not more than 23 nm.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Yoshihiko Kanzawa, Satoru Mitani, Zhiqiang Wei, Takeshi Takagi, Koji Katayama
  • Patent number: 8445886
    Abstract: A nonvolatile memory element comprises a first electrode (103); a second electrode (105); and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (105), resistance values of the resistance variable layer reversibly changing in response to electric signals applied between the electrodes (103, 105); the resistance variable layer (104) including a first tantalum oxide layer (107) comprising a first tantalum oxide and a second tantalum oxide layer (108) comprising a second tantalum oxide which is different in oxygen content from the first tantalum oxide, the first tantalum oxide layer and the second tantalum oxide layer being stacked together, and being configured such that 0<x<2.5 is satisfied when the first tantalum oxide is expressed as TaOx and x<y?2.5 is satisfied when the second tantalum oxide is expressed as TaOy; and the second electrode (105) being in contact with the second tantalum oxide layer (108) and comprising platinum and tantalum.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: May 21, 2013
    Assignee: Panasonic Corporation
    Inventors: Satoru Fujii, Koji Arita, Satoru Mitani, Takumi Mikawa
  • Publication number: 20130112936
    Abstract: A variable resistance element including: a first electrode; a second electrode; and a variable resistance layer having a resistance value which reversibly changes according to electrical signals applied, wherein the variable resistance layer includes a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first transition metal oxide layer, the second electrode has a single needle-shaped part at the interface with the second variable resistance layer, and the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers the needle-shaped part.
    Type: Application
    Filed: January 18, 2012
    Publication date: May 9, 2013
    Applicant: Panasonic Corporation
    Inventors: Zhiqiang WEI, Takeshi Takagi, Satoru Mitani, Yoshio Kawashima, Ichirou Takahashi