Abstract: On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.

Abstract: On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.

Abstract: On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.

Abstract: In the disclosed semiconductor integrated circuit, a plurality of power supply terminals of the logic circuit block are connected to the actual power supply line via the leak current cut-off circuit. When the logic circuit block is to be activated, the delay control circuit controls the leak current cut-off circuit to electrically connect the power supply terminal to the actual power supply line with a delay of the predetermined time. Therefore, when the logic circuit block is activated, voltage drop of the actual power supply line can be lowered to a small value and erroneous operation of the other logic circuit block in the activated condition due to the power supply noise can be prevented.

Abstract: A semiconductor integrated circuit device has a high-threshold N-channel type MIS field effect transistor and a load circuit. The high-threshold N-channel type MIS field effect transistor is connected between a real high-potential power supply line and a pseudo high-potential power supply line. The load circuit has a low-threshold P-channel type MIS field effect transistor and a low-threshold N-channel type MIS field effect transistor. A first power supply terminal of the load circuit is connected to the pseudo high-potential power supply line, and a second power supply terminal of the load circuit is connected to a real low-potential power supply line.

Abstract: In the disclosed semiconductor integrated circuit, a plurality of power supply terminals of the logic circuit block are connected to the actual power supply line via the leak current cut-off circuit. When the logic circuit block is to be activated, the delay control circuit controls the leak current cut-off circuit to electrically connect the power supply terminal to the actual power supply line with a delay of the predetermined time. Therefore, when the logic circuit block is activated, voltage drop of the actual power supply line can be lowered to a small value and erroneous operation of the other logic circuit block in the activated condition due to the power supply noise can be prevented.

Abstract: On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.

Abstract: It is judged before encoding sound data whether one frame of the sound data for transmission is silent, and if judged as silent, switching circuits 202 and 203, which is for stopping/resuming electric power supply to a circuit 201 for encoding the sound data, are turned off by a power control circuit 30A during an encoding period of one frame. The power control circuit 30A consists of a counter 32 initialized by a frame synchronization pulse FSYNC and counting a sound sampling clock CLKS, a constant setting part 34, a comparator 33 activating a coincident signal EQ when a count of the counter 32 coincides with a set value, and a flip-flop 31 set by a no-voice detect pulse NOV and reset when EQ is activated.