Patents by Inventor Satoru Mizuta

Satoru Mizuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9577654
    Abstract: In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: February 21, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Masashi Kijima, Satoru Mizuta, Tsutomu Tanii, Hiroyuki Matsunami
  • Publication number: 20160373124
    Abstract: In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter.
    Type: Application
    Filed: December 21, 2015
    Publication date: December 22, 2016
    Inventors: Masashi Kijima, Satoru Mizuta, Tsutomu Tanii, Hiroyuki Matsunami
  • Patent number: 8957795
    Abstract: An analog-to-digital conversion device includes: an analog-to-digital converter that receives an analog voltage and converts the analog voltage into a digital value to output the converted digital value; and an offset correction unit that arithmetically operates an offset correction value based on a first digital value and a second digital value, the first digital value being to be output from the analog-to-digital converter by the analog-to-digital converter receiving a first analog voltage, the second digital value being to be output from the analog-to-digital converter by the analog-to-digital converter receiving a second analog voltage, the second analog voltage having a voltage value different from that of the first analog voltage, in which after the arithmetic operation of the offset correction value, the analog-to-digital converter outputs a digital value obtained by subtracting the offset correction value from the converted digital value.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Youji Kawano, Motoki Shimozono, Youichi Satou, Kazuhiro Konomoto, Satoru Mizuta, Masashi Kijima
  • Publication number: 20140240151
    Abstract: An analog-to-digital conversion device includes: an analog-to-digital converter that receives an analog voltage and converts the analog voltage into a digital value to output the converted digital value; and an offset correction unit that arithmetically operates an offset correction value based on a first digital value and a second digital value, the first digital value being to be output from the analog-to-digital converter by the analog-to-digital converter receiving a first analog voltage, the second digital value being to be output from the analog-to-digital converter by the analog-to-digital converter receiving a second analog voltage, the second analog voltage having a voltage value different from that of the first analog voltage, in which after the arithmetic operation of the offset correction value, the analog-to-digital converter outputs a digital value obtained by subtracting the offset correction value from the converted digital value.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Youji KAWANO, Motoki SHIMOZONO, Youichi SATOU, Kazuhiro KONOMOTO, Satoru MIZUTA, Masashi KIJIMA
  • Patent number: 6124080
    Abstract: A first layer (2) and a second layer (3) are formed on a substrate (1). The first layer is made of a resist against a groove-sculpturing etchant used in etching the substrate while the second layer is made of an anti-corrosive material against dry etching. The second layer is at first patterned into a patterned second layer (3a) in the form of a groove-sculpturing mask pattern (8). With the patterned second layer used as a mask, the first layer is etched and patterned into a patterned first layer (2a) in the form of the above-mentioned mask pattern. With the patterned first layer used as a mask, the substrate is etched to form a groove (9).
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: September 26, 2000
    Assignee: NEC Corporation
    Inventors: Satoru Mizuta, Hiroshi Nishimoto
  • Patent number: 6108480
    Abstract: A first layer (2) and a second layer (3) are formed on a substrate (1). The first layer is made of a resist against a groove-sculpturing etchant used in etching the substrate while the second layer is made of an anti-corrosive material against dry etching. The second layer is at first patterned into a patterned second layer (3a) in the form of a groove-sculpturing mask pattern (8). With the patterned second layer used as a mask, the first layer is etched and patterned into a patterned first layer (2a) in the form of the above-mentioned mask pattern. With the patterned first layer used as a mask, the substrate is etched to form a groove (9).
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: August 22, 2000
    Assignee: NEC Corporation
    Inventors: Satoru Mizuta, Hiroshi Nishimoto
  • Patent number: 5961683
    Abstract: A first layer (2) and a second layer (3) are formed on a substrate (1). The first layer is made of a resist against a groove-sculpturing etchant used in etching the substrate while the second layer is made of an anti-corrosive material against dry etching. The second layer is at first patterned into a patterned second layer (3a) in the form of a groove-sculpturing mask pattern (8). With the patterned second layer used as a mask, the first layer is etched and patterned into a patterned first layer (2a) in the form of the above-mentioned mask pattern. With the patterned first layer used as a mask, the substrate is etched to form a groove (9).
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: October 5, 1999
    Assignee: NEC Corporation
    Inventors: Satoru Mizuta, Hiroshi Nishimoto
  • Patent number: 5488324
    Abstract: In a detection circuit, a voltage-conversion circuit is supplied with a first voltage signal indicative of the state of an object circuit and produces an output current in response thereto, a detection circuit is supplied with a second voltage signal and detects the state of the object circuit in response thereto, and a clamping circuit, having an input terminal, is supplied at the input terminal thereof with the output current of the voltage-current conversion circuit and clamps the voltage at the input terminal thereof, and thus the output voltage of the voltage-current conversion circuit, at a predetermined level. The clamping circuit further produces the second voltage signal, which is supplied to the detection circuit, in response to the output current of the voltage-current conversion circuit and such that the second voltage signal has a magnitude proportional to the first voltage signal.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: January 30, 1996
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Satoru Mizuta, Katsuya Shimizu