Abstract: According to one embodiment, a PLL circuit generates a first signal of 1/m times from a reference clock and a second signal of 1/n times from an output of an oscillator, obtains a quantized phase difference corresponding to a shift amount between the both signals, integrates the phase difference, predicts a control value for the oscillator based on the integrated value, converts the predicted control value into an analog value. Sequential integration is performed for the phase difference until the polarity of the phase difference is reversed from negative to positive and then from positive to negative again, or until the polarity is reversed from positive to negative and then from negative to positive again, a predictive weight value is generated by multiplying the integrated value by a predictive coefficient value of optional ratio, and the control value is obtained by adding the predictive weight value to the integrated value.

Abstract: According to one embodiment, a malfunction predicting unit includes a level reduction unit, a first buffer gate unit, a second buffer gate unit, a comparator unit and a processing unit. The level reduction unit reduces an input digital signal to generate a level-reduced signal. The first buffer gate unit generates a first output signal. The first output signal has first or second level if the digital signal is or is not higher than a preset threshold level, respectively. The second buffer gate unit generates a second output signal. The second output signal has the first or second level if the level-reduced signal is or is not higher than the preset threshold level, respectively. The comparator unit compares the first and second output signals to generate a comparison result. The processing unit determines whether a malfunction will soon occur, based on the comparison result.

Abstract: According to one embodiment, a malfunction predicting unit includes a level reduction unit, a first buffer gate unit, a second buffer gate unit, a comparator unit and a processing unit. The level reduction unit reduces an input digital signal to generate a level-reduced signal. The first buffer gate unit generates a first output signal. The first output signal has first or second level if the digital signal is or is not higher than a preset threshold level, respectively. The second buffer gate unit generates a second output signal. The second output signal has the first or second level if the level-reduced signal is or is not higher than the preset threshold level, respectively. The comparator unit compares the first and second output signals to generate a comparison result. The processing unit determines whether a malfunction will soon occur, based on the comparison result.

Abstract: According to one embodiment, a PLL circuit generates a first signal of 1/m times from a reference clock and a second signal of 1/n times from an output of an oscillator, obtains a quantized phase difference corresponding to a shift amount between the both signals, integrates the phase difference, predicts a control value for the oscillator based on the integrated value, converts the predicted control value into an analog value. Sequential integration is performed for the phase difference until the polarity of the phase difference is reversed from negative to positive and then from positive to negative again, or until the polarity is reversed from positive to negative and then from negative to positive again, a predictive weight value is generated by multiplying the integrated value by a predictive coefficient value of optional ratio, and the control value is obtained by adding the predictive weight value to the integrated value.