Patents by Inventor Satoru Ohshita

Satoru Ohshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250078895
    Abstract: An operation method of a semiconductor device that performs data writing and correction processing is provided. The operation method is for a semiconductor device including a control circuit, a first circuit, a second circuit, a wiring, a cell, and a converter circuit. In the operation method, first, the control circuit transmits, to the first circuit, a first signal corresponding to the value of first data. Next, the first circuit outputs, to the wiring, a first current with an amount corresponding to the first signal. Moreover, the cell retains a first potential corresponding to the amount of first current. Then, the cell makes a second current corresponding to the first potential flow from the wiring, and the converter circuit outputs a second signal corresponding to the amount of second current. Next, the second circuit obtains a difference value between a value corresponding to the second signal and the value of the first data. If the difference value is 0, the operation is terminated.
    Type: Application
    Filed: January 25, 2023
    Publication date: March 6, 2025
    Inventors: Hidefumi RIKIMARU, Yoshiyuki KUROKAWA, Satoru OHSHITA
  • Patent number: 12245485
    Abstract: A high-resolution display apparatus having a function of sensing light is provided. The display apparatus includes a display portion in which a first arrangement pattern and a second arrangement pattern are repeatedly arranged in this order in a first direction. In the first arrangement pattern, a first subpixel, a second subpixel, and a third subpixel are repeatedly arranged in this order in a second direction. In the second arrangement pattern, a fourth subpixel and a fifth subpixel are repeatedly arranged in this order in the second direction. The first to fourth subpixels each include a light-emitting device. The fifth subpixel includes a light-receiving device.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 4, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Kouhei Toyotaka, Satoru Ohshita, Daisuke Kubota
  • Patent number: 12207462
    Abstract: A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: January 21, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuki Tsuda, Hiromichi Godo, Satoru Ohshita, Hitoshi Kunitake
  • Patent number: 12205625
    Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first gate and a first back gate, and the second transistor includes a second gate and a second back gate. A gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of, when being in an off state, retaining a first potential corresponding to first data. The second transistor has a function of making an output current flow between a source and a drain of the second transistor.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: January 21, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Yoshiyuki Kurokawa, Kazuki Tsuda, Satoru Ohshita
  • Patent number: 12200950
    Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: January 14, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Yoshiyuki Kurokawa, Kouhei Toyotaka, Kazuki Tsuda, Satoru Ohshita, Hidefumi Rikimaru
  • Patent number: 12193236
    Abstract: A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: January 7, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hitoshi Kunitake, Satoru Ohshita, Kazuki Tsuda, Tatsuya Onuki
  • Patent number: 12082391
    Abstract: A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 3, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Ohshita, Hitoshi Kunitake, Kazuki Tsuda
  • Publication number: 20240256037
    Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.
    Type: Application
    Filed: March 4, 2024
    Publication date: August 1, 2024
    Inventors: Yoshiyuki KUROKAWA, Hiromichi GODO, Kouhei TOYOTAKA, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240237435
    Abstract: A semiconductor device with reduced circuit area is provided. The semiconductor device includes first and second cell arrays and a first converter circuit. The first cell array includes a first cell and a second cell in the same row, and the second cell array includes third and fourth cells in the same row. The first cell is electrically connected to first and second wirings, the second cell is electrically connected to the first and third wirings, the third cell is electrically connected to fourth and sixth wirings, and the fourth cell is electrically connected to fifth and seventh wirings. The sixth wiring is electrically connected to the seventh wiring. The first to fourth cells each have a function of outputting current corresponding to a product of retained data and input data. Specifically, the first cell, the second cell, the third cell, and the fourth cell output current to the second wiring, the third wiring, the sixth wiring, and the seventh wiring, respectively.
    Type: Application
    Filed: April 20, 2022
    Publication date: July 11, 2024
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuki TSUDA, Hidefumi RIKIMARU, Satoru OHSHITA, Hiromichi GODO, Yoshiyuki KUROKAWA
  • Publication number: 20240231756
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 11, 2024
    Inventors: Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240234310
    Abstract: A novel semiconductor device is provided. In reservoir computing using an input layer, a reservoir layer, and an output layer, variation in threshold voltage between transistors is used as a weight used for product arithmetic processing. Two transistors are provided in one product arithmetic circuit and data u is supplied to gates of the two transistors. Drain current of each of the transistors is determined by the data u and the threshold voltage of the transistor. The difference between the drain currents corresponds to a product arithmetic result. The difference between the drain currents is converted into voltage to be output. A plurality of product arithmetic circuits are connected in parallel to form a product-sum arithmetic circuit.
    Type: Application
    Filed: May 13, 2022
    Publication date: July 11, 2024
    Inventors: Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Kouhei TOYOTAKA, Satoru OHSHITA, Hidefumi RIKIMARU, Hideki UOCHI
  • Publication number: 20240237374
    Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user.
    Type: Application
    Filed: February 24, 2022
    Publication date: July 11, 2024
    Inventors: Hiromichi GODO, Yoshiyuki KUROKAWA, Kouhei TOYOTAKA, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240138167
    Abstract: An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user.
    Type: Application
    Filed: February 24, 2022
    Publication date: April 25, 2024
    Inventors: Hiromichi GODO, Yoshiyuki KUROKAWA, Kouhei TOYOTAKA, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20240134605
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a cell array performing a product-sum operation of a first layer and a product-sum operation of a second layer in an artificial neural network, a first circuit from which first data is input to the cell array, and a second circuit to which second data is output from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In a first period, the first region is supplied with the t-th (t is a natural number greater than or equal to 2) first data from the first circuit and outputs the t-th second data according to the product-sum operation of the first layer to the second circuit. In the first period, the second region is supplied with the (t+1)-th first data from the first circuit and outputs the (t+1)-th second data according to the product-sum operation of the second layer to the first circuit.
    Type: Application
    Filed: February 24, 2022
    Publication date: April 25, 2024
    Inventors: Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Patent number: 11921919
    Abstract: To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Hiromichi Godo, Kouhei Toyotaka, Kazuki Tsuda, Satoru Ohshita, Hidefumi Rikimaru
  • Publication number: 20230386544
    Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first gate and a first back gate, and the second transistor includes a second gate and a second back gate. A gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of, when being in an off state, retaining a first potential corresponding to first data. The second transistor has a function of making an output current flow between a source and a drain of the second transistor.
    Type: Application
    Filed: September 7, 2021
    Publication date: November 30, 2023
    Inventors: Hiromichi GODO, Yoshiyuki KUROKAWA, Kazuki TSUDA, Satoru OHSHITA
  • Publication number: 20230369329
    Abstract: A semiconductor device with low power consumption is provided. The semiconductor device includes a first layer and a second layer. The first layer includes a first cell and a first to a third circuit, and the second layer includes a second cell and a fourth and a fifth circuit. The first, second, and fourth circuits each have a function of converting digital data into analog current. The first cell calculates a product of a value from the first current and a value from the second circuit and inputs a calculation result into a third circuit as current. The third circuit generates analog current from the input current. The second cell calculates a product of a value from the third circuit and a value from the fourth circuit and inputs a calculation result into the fifth circuit as current. The fifth circuit generates analog current from the input current.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 16, 2023
    Inventors: Yoshiyuki KUROKAWA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20230352090
    Abstract: A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.
    Type: Application
    Filed: December 28, 2020
    Publication date: November 2, 2023
    Inventors: Kazuki TSUDA, Hiromichi GODO, Satoru OHSHITA, Hitoshi KUNITAKE, Satoru OKAMOTO
  • Publication number: 20230353163
    Abstract: A novel semiconductor device is provided. An analog signal is converted into a digital signal using a comparison portion comparing two current values, a control portion, and a current output digital-analog conversion portion. The control portion has a function of generating a sign bit showing a magnitude relation between the two current values, a function of converting a difference between the two current values into a digital signal by successive approximation, and a function of outputting the sign bit and the digital signal.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 2, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro KANEMURA, Yoshiyuki KUROKAWA, Hiromichi GODO, Kazuki TSUDA, Satoru OHSHITA, Hidefumi RIKIMARU
  • Publication number: 20230317176
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes memory layers and a driver circuit layer. The memory layers are stacked over the driver circuit layer and each include a memory cell array including a plurality of memory cells. Writing or reading of data to or from one of the memory cells is controlled with a write word line, a read word line, a write bit line, and a read bit line. The driver circuit layer includes a driver circuit portion configured to drive the write word line, the read word line, the write bit line, and the read bit line; and an arithmetic circuit portion. The driver circuit portion includes a plurality of driver circuits configured to control data writing or reading on the memory cell array basis. The arithmetic circuit portion is a circuit configured to perform arithmetic processing using the data retained in the memory cell array provided in each of the memory layers and read through the driver circuit portion.
    Type: Application
    Filed: March 23, 2023
    Publication date: October 5, 2023
    Inventors: Yoshiyuki KUROKAWA, Satoru OHSHITA, Hidefumi RIKIMARU