Abstract: A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data.

Abstract: A nonvolatile semiconductor memory, includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a code output circuit that outputs any one of a plurality of codes to the voltage generator circuit, wherein the plurality of codes includes a first code and a second code, wherein the second code is different from the first code, wherein, in a first state, the code output circuit outputs the first code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the first code, and wherein, in a second state, the code output circuit outputs the second code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the second code.

Abstract: A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data.

Abstract: A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data.

Abstract: A nonvolatile semiconductor memory, includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a code output circuit that outputs any one of a plurality of codes to the voltage generator circuit, wherein the plurality of codes includes a first code and a second code, wherein the second code is different from the first code, wherein, in a first state, the code output circuit outputs the first code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the first code, and wherein, in a second state, the code output circuit outputs the second code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the second code.

Abstract: A nonvolatile semiconductor memory includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a trimming code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a trimming code output circuit that outputs any one of plural trimming codes to the voltage generator circuit. The plural trimming codes include a test trimming code in addition to an appropriate trimming code for generating a desired drive voltage. The test trimming code is different from the appropriate trimming code, and used only in the test state. In the test state, the trimming code output circuit outputs the test trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the test trimming code.

Abstract: A nonvolatile semiconductor memory includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a trimming code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a trimming code output circuit that outputs any one of plural trimming codes to the voltage generator circuit. The plural trimming codes include a test trimming code in addition to an appropriate trimming code for generating a desired drive voltage. The test trimming code is different from the appropriate trimming code, and used only in the test state. In the test state, the trimming code output circuit outputs the test trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the test trimming code.

Abstract: A power-source potential control circuit has: an output terminal outputting a control signal to a power-source generating device which generates a power-source potential in accordance with the control signal; an input terminal connected to an output of the power-source generating device; and a control unit configured to make a comparison between a trimming potential depending on a first potential at the input terminal and a predetermined reference potential and to output the control signal corresponding to a result of the comparison. In a trimming operation mode, the control unit changes the trimming potential in accordance with the result of the comparison.

Abstract: A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data.

Abstract: A power-source potential control circuit has: an output terminal outputting a control signal to a power-source generating device which generates a power-source potential in accordance with the control signal; an input terminal connected to an output of the power-source generating device; and a control unit configured to make a comparison between a trimming potential depending on a first potential at the input terminal and a predetermined reference potential and to output the control signal corresponding to a result of the comparison. In a trimming operation mode, the control unit changes the trimming potential in accordance with the result of the comparison.

Abstract: A booster is provided with first to k-th (k is an even number) transistors connected to one another in series, first to k-th capacitors each having an end connected to the gate and source of each of the first to k-th transistors, and a clock driver which supplies clock signals out of phase with one another to the other ends of the first to k-th capacitors. The clock driver simultaneously supplies low-level clock signals to two or more adjacent capacitors out of the first to k-th capacitors.

Abstract: A booster is provided with first to k-th (k is an even number) transistors connected to one another in series, first to k-th capacitors each having an end connected to the gate and source of each of the first to k-th transistors, and a clock driver which supplies clock signals out of phase with one another to the other ends of the first to k-th capacitors. The clock driver simultaneously supplies low-level clock signals to two or more adjacent capacitors out of the first to k-th capacitors.

Abstract: A semiconductor memory device comprises a plurality of sub bit lines 12a and 12b to which a plurality of memory cell transistors 13a through 13h are connected. The sub bit lines are selectively connected to a main bit line 11a. The sub and main bit lines are made of metallic material.

Abstract: Disclosed herein is a non-volatile semiconductor memory device comprising a mode signal output means for outputting a mode signal for conducting flash programming or flash erasing, a group selection signal output means for outputting a group selection signal for selecting a row decoding group, a first selection means for selecting the row decoding group controlling the word line in accordance with 10 the group selection signal, and a second selection means selecting the word line corresponding to the memory cell from a plurality of the word lines controlled by the row decoding group selected by the first selection means. In the present inventions the time required for the flash programming and the flash erasing can be reduced without the addition of a further element and the chip areas can be reduced.

Abstract: A power source circuit for a flash memory includes a positive circuit section for generating a positive voltage source, a source follower transistor for converting the impedance of the first voltage source, a negative circuit section for generating a negative voltage source while maintaining a voltage difference between the output of the source follower transistor and the negative voltage source at a first reference potential. The positive circuit section includes a voltage compensating transistor having a threshold voltage equal to the threshold of the source follower transistor.

Abstract: A semiconductor device has a plurality of power supply circuits whose generated voltages are different from each other, and a plurality of internal circuits whose operating voltages are different from each other. The power supply circuits and the internal circuits are interconnected by power lines with respective power supply switches inserted therein. The power lines are connected to a single external terminal by respective control lines with respective external switches inserted therein. The power supply circuits and the internal circuits can be tested from the single external terminal.