Abstract: An antenna apparatus for use in a transmitter or a receiver in a communication system. The antenna apparatus includes: a dielectric substrate having a conductor layer on one of surfaces; and a slot antenna including an antenna electrode formed on the one surface and disposed substantially at the center, a grounded conductive surface surrounding the antenna electrode, and a slot transmission line made by a gap between the antenna electrode and the grounded conductive surface.

Abstract: A signal processing device includes a correction circuit configured to correct the distortion of the duty cycle in a data signal having different occurrence probabilities of 0 and 1.

Abstract: There is provided a wireless communication apparatus configured to perform wireless communications with a counterpart apparatus by use of a data frame including a data transmission indication period and a data transmission period following the indication period. In the apparatus a normal power state and a low power consumption state are set as the operating states, and a normal power mode and a low power consumption mode are set as the power management modes. Further, in the normal power mode, the wireless communication apparatus is operated in the normal power state; and in the low power consumption mode, the wireless communication apparatus is operated in the normal power state during the data transmission indication period and in the low power consumption state during the data transmission period.

Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Abstract: An antenna apparatus for use in a transmitter or a receiver in a communication system. The antenna apparatus includes: a dielectric substrate having a conductor layer on one of surfaces; and a slot antenna including an antenna electrode formed on the one surface and disposed substantially at the center, a grounded conductive surface surrounding the antenna electrode, and a slot transmission line made by a gap between the antenna electrode and the grounded conductive surface.

Abstract: A signal processing device includes a correction circuit configured to correct the distortion of the duty cycle in a data signal having different occurrence probabilities of 0 and 1.

Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then run-length counted with a virtual channel clock so as to extract data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.

Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Abstract: There is provided a wireless communication apparatus configured to perform wireless communications with a counterpart apparatus by use of a data frame including a data transmission indication period and a data transmission period following the indication period. In the apparatus a normal power state and a low power consumption state are set as the operating states, and a normal power mode and a low power consumption mode are set as power management modes. Further, in the normal power mode, the wireless communication apparatus is operated in the normal power state; and in the low power consumption mode, the wireless communication apparatus is operated in the normal power state during the data transmission indication period and in the low power consumption state during the data transmission period.

Abstract: A wireless communication apparatus able to shorten a connection time between wireless communication apparatuses, including a wireless module activated after the end of download of firmware and becoming able to communicate with another apparatus for communication and a system control unit able to download the firmware after activation, wherein the wireless module includes a memory unit able to hold storage data even when power is turned off, and the system control unit downloads the firmware into the memory unit of the wireless module when the power of the wireless module is turned on and a communication system, a wireless communication method, and a program related to the same.

Abstract: In a digital PLL system, instead of measuring a binarized playback RF signal with a high frequency clock, pulse-length data is generated by using N phase clocks (for example, 16 phase clocks). The pulse-length data is then counted with a virtual channel clock so as to extract run-length data. In this digital PLL system, the number of changing points of an asynchronous signal during an interval between adjacent clocks of the N phase clocks is detected so as to determine phase errors from the detected number of changing points. Phase errors are also determined from the timing relationship between changing points of a signal synchronized with the N phase clocks and each clock of the N phase clocks.

Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.