Patents by Inventor Satoru Sekine

Satoru Sekine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11174745
    Abstract: A stator blade of an embodiment includes: a blade effective part having hollow portions; an outer shroud having an outer plate flange portion provided on a radial-direction outer side of the blade effective part, and a pair of outer mounting portions provided in a circumferential direction on a front edge side and a rear edge side; an inner shroud having an inner plate flange portion provided on a radial-direction inner side of the blade effective part; cooling medium introduction passages which introduce a cooling medium via opening portions formed in the outer plate flange portion and passing through the outer plate flange portion in a radial direction, to the hollow portions; and a cooling medium introduction passage formed in a direction along a surface of the outer plate flange portion in a wall thickness of the outer plate flange portion, which introduces a cooling medium to the hollow portion.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 16, 2021
    Assignee: Toshiba Energy Systems & Solutions Corporation
    Inventors: Asako Inomata, Shinji Tanigawa, Iwataro Sato, Hideyuki Maeda, Satoru Sekine, Kazutaka Tsuruta
  • Publication number: 20200131923
    Abstract: A stator blade of an embodiment includes: a blade effective part having hollow portions; an outer shroud having an outer plate flange portion provided on a radial-direction outer side of the blade effective part, and a pair of outer mounting portions provided in a circumferential direction on a front edge side and a rear edge side; an inner shroud having an inner plate flange portion provided on a radial-direction inner side of the blade effective part; cooling medium introduction passages which introduce a cooling medium via opening portions formed in the outer plate flange portion and passing through the outer plate flange portion in a radial direction, to the hollow portions; and a cooling medium introduction passage formed in a direction along a surface of the outer plate flange portion in a wall thickness of the outer plate flange portion, which introduces a cooling medium to the hollow portion.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 30, 2020
    Applicant: Toshiba Energy Systems & Solutions Corporation
    Inventors: Asako INOMATA, Shinji TANIGAWA, Iwataro SATO, Hideyuki MAEDA, Satoru SEKINE, Kazutaka TSURUTA
  • Patent number: 10563529
    Abstract: According to an embodiment, a turbine comprises: a cylindrical casing; and turbine stator blades arranged in the casing along a circumferential direction. The turbine stator blades each includes: a blade effective part; a coolant flow path through which a coolant flows in the blade effective part to cool the blade effective part; an outer ring sidewall provided on an outer periphery of the blade effective part; an inner ring sidewall provided on an inner periphery of the blade effective part; and a contact part provided at an end part of the inner ring sidewall with at least part thereof being along a flow direction of a working fluid, coming into contact with the inner ring sidewall of the adjacent blade during operation, and separating from the inner ring sidewall of the adjacent blade when the operation is stopped.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: February 18, 2020
    Assignee: Toshiba Energy Systems & Solutions Corporation
    Inventors: Kazutaka Tsuruta, Iwataro Sato, Hideyuki Maeda, Satoru Sekine
  • Patent number: 10550698
    Abstract: A turbine 10 includes: a turbine rotor having a rotor main body including a hollow part into which a cooling fluid flows, and a plurality of rotor wheels arranged in an axial direction of the rotor main body and protruding from the rotor main body. A cooling-fluid introducing passage extending from the hollow part in a direction intersecting with the axial direction of the rotor main body is formed in the rotor main body so as to allow the cooling fluid in the hollow part to flow through the cooling-fluid introducing passage and then to flow around the rotor wheel to be conducted to the working-fluid flow passage. A flow-rate control plug regulating a flow rate of the cooling fluid flowing through the cooling-fluid introducing passage is disposed in the cooling-fluid introducing passage.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: February 4, 2020
    Assignee: Toshiba Energy Systems & Solutions Corporation
    Inventors: Asako Inomata, Iwataro Sato, Hideyuki Maeda, Satoru Sekine, Kazutaka Tsuruta, Takeo Suga
  • Publication number: 20190120070
    Abstract: According to an embodiment, a turbine comprises: a cylindrical casing; and turbine stator blades arranged in the casing along a circumferential direction. The turbine stator blades each includes: a blade effective part; a coolant flow path through which a coolant flows in the blade effective part to cool the blade effective part; an outer ring sidewall provided on an outer periphery of the blade effective part; an inner ring sidewall provided on an inner periphery of the blade effective part; and a contact part provided at an end part of the inner ring sidewall with at least part thereof being along a flow direction of a working fluid, coming into contact with the inner ring sidewall of the adjacent blade during operation, and separating from the inner ring sidewall of the adjacent blade when the operation is stopped.
    Type: Application
    Filed: September 7, 2017
    Publication date: April 25, 2019
    Applicant: Toshiba Energy Systems & Solutions Corporation
    Inventors: Kazutaka TSURUTA, Iwataro SATO, Hideyuki MAEDA, Satoru SEKINE
  • Publication number: 20160376890
    Abstract: A turbine 10 includes: a turbine rotor having a rotor main body including a hollow part into which a cooling fluid flows, and a plurality of rotor wheels arranged in an axial direction of the rotor main body and protruding from the rotor main body. A cooling-fluid introducing passage extending from the hollow part in a direction intersecting with the axial direction of the rotor main body is formed in the rotor main body so as to allow the cooling fluid in the hollow part to flow through the cooling-fluid introducing passage and then to flow around the rotor wheel to be conducted to the working-fluid flow passage. A flow-rate control plug regulating a flow rate of the cooling fluid flowing through the cooling-fluid introducing passage is disposed in the cooling-fluid introducing passage.
    Type: Application
    Filed: September 8, 2016
    Publication date: December 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Asako INOMATA, Iwataro SATO, Hideyuki MAEDA, Satoru SEKINE, Kazutaka TSURUTA, Takeo SUGA
  • Patent number: 8008959
    Abstract: A flip-flop circuit operates by a first clock signal whose amplitude is smaller than that of input data D. A pair of transistors receive the input data D and the reversed input data *D, respectively, to latch the input data D. An activation circuit activates the pair of transistors in a conduction state. A control circuit receives the first clock signal and sets the activation circuit to a conduction state for a predetermined time period starting from an edge timing of the received first clock signal. The control circuit increases the amplitude of the first clock signal and sets the activation circuit in a conduction state by using a second clock signal which is the first clock signal with the increased amplitude.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: August 30, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Satoru Sekine, Shinji Furuichi
  • Patent number: 7746138
    Abstract: A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: June 29, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Satoru Sekine, Yoshitaka Ueda, Takashi Asano, Shinji Furuichi, Atsushi Wada
  • Publication number: 20090231008
    Abstract: A flip-flop circuit operates by a first clock signal whose amplitude is smaller than that of input data D. A pair of transistors receive the input data D and the reversed input data *D, respectively, to latch the input data D. An activation circuit activates the pair of transistors in a conduction state. A control circuit receives the first clock signal and sets the activation circuit to a conduction state for a predetermined time period starting from an edge timing of the received first clock signal. The control circuit increases the amplitude of the first clock signal and sets the activation circuit in a conduction state by using a second clock signal which is the first clock signal with the increased amplitude.
    Type: Application
    Filed: February 13, 2009
    Publication date: September 17, 2009
    Inventors: Satoru Sekine, Shinji Furuichi
  • Publication number: 20080218235
    Abstract: A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 11, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Satoru SEKINE, Yoshitaka Ueda, Takashi Asano, Shinji Furuichi, Atsushi Wada
  • Publication number: 20080030250
    Abstract: A pair of transistors receive the input of signals of input data and the inverted input data. An activation circuit, which is provided between the pair of transistors and fixed potential, activates the pair of transistors in a conduction state. A clock control circuit receives a clock signal and sets the activation circuit to a conduction state for a predetermined period starting from an edge timing of the clock signal. The activation circuit includes a first activation transistor and a second activation transistor which are connected in cascade with each other. The clock control circuit turns on both the first activation transistor and the second transistor for the predetermined period starting from the edge timing of the clock signal, and turns off at least one of the first activation transistor and the second activation transistor for a period other than the predetermined period.
    Type: Application
    Filed: March 29, 2007
    Publication date: February 7, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shinji Furuichi, Satoru Sekine
  • Publication number: 20060002258
    Abstract: An electronic apparatus and a method for ejecting a medium are provided that can ensure identification of eject keys for media even when the display of a touch panel surface is difficult to view. In the electronic apparatus, a touch panel 50 is slid to open a plurality of medium insertion/ejection ports 61 to 63, so that the predetermined medium (CD, DVD, MD) can be inserted therein and ejected therefrom. When the medium insertion/ejection port is opened, a touch panel surface is divided into areas, and the divisional areas SAR1 to SAR3 are allocated to touch switches EJK1 to EJK3 for ejection of the respective predetermined media. When the touch panel surface is touched, it is detected which touch switch is turned on, and then the medium corresponding to the touch switch turned on is ejected.
    Type: Application
    Filed: June 23, 2005
    Publication date: January 5, 2006
    Inventors: Takashi Nakamura, Satoru Sekine
  • Publication number: 20050212787
    Abstract: In an active matrix display apparatus, the drive transistor to drive an OLED self-corrects the operation timing of the drive transistor. A correction transistor controls on and off of the self-correction. The drive circuit self-corrects the operation of the drive transistor by generating a luminance signal which is corrected based on a predetermined signal delivered temporarily and an operation threshold value. The current flowing to the OLED is controlled by gradually changing the voltage of luminance signal from a ramp signal line. After the luminance signal for one frame is inputted to each pixel, the same luminance signal for one frame is inputted to the each pixel in a reversed scanning direction. One frame period is divided into a plurality of subframe periods and the data control circuit inputs respectively the same luminance signal to each pixel in the plurality of subframe periods.
    Type: Application
    Filed: March 21, 2005
    Publication date: September 29, 2005
    Inventors: Yukihiro Noguchi, Satoru Sekine, Kouiti Yamada, Shoichiro Matsumoto
  • Patent number: 6930906
    Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell includes a bit line, a word line arranged to intersect with the bit line, and a memory cell, which is arranged between the bit line and the word line an includes a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: August 16, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Matsushita, Yoh Takano, Satoru Sekine
  • Publication number: 20030174532
    Abstract: A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell is provided. This ferroelectric memory comprises a bit line, a word line arranged to intersect with the bit line and a diode, arranged between the bit line and the word line, including a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.
    Type: Application
    Filed: March 14, 2003
    Publication date: September 18, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Shigeharu Matsushita, Yoh Takano, Satoru Sekine