Patents by Inventor Satoru Shimada
Satoru Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100102382Abstract: The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N? type semiconductor layer. A thin silicon oxide film is formed on a region of the N? type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N? type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance.Type: ApplicationFiled: September 26, 2008Publication date: April 29, 2010Applicant: SANYO Electric Co., Ltd.Inventors: Satoru Shimada, Yoshikazu Yamaoka, Kazunori Fujita, Tomonori Tabe
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Patent number: 7692187Abstract: The present invention encompasses an organic field-effect transistor comprising an n-type organic semiconductor formed of a fullerene derivative having a fluorinated alkyl group which is expressed by the following chemical formula (wherein at least any one of R1, R2 and R3 is a perfluoro alkyl group or a partially-fluorinated semifluoro alkyl group each having a carbon number of 1 to 20), and a field-effect transistor production method comprising forming an organic semiconductor layer using the fullerene derivative by a solution process, and subjecting the organic semiconductor layer to a heat treatment in an atmosphere containing nitrogen or argon or in vacuum to provide enhanced characteristics to the organic semiconductor layer. The present invention makes it possible to form an organic semiconductor layer by a solution process and provide an organic field-effect transistor excellent in electron mobility and on-off ratio and capable of operating even in an ambient air atmosphere.Type: GrantFiled: March 20, 2007Date of Patent: April 6, 2010Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Masayuki Chikamatsu, Atsushi Itakura, Tatsumi Kimura, Satoru Shimada, Yuji Yoshida, Reiko Azumi, Kiyoshi Yase
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Publication number: 20100059816Abstract: The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N? type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage.Type: ApplicationFiled: September 26, 2008Publication date: March 11, 2010Applicant: SANYO Electric Co., Ltd.Inventors: Satoru Shimada, Yoshikazu Yamaoka, Kazunori Fujita, Tomonori Tabe
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Patent number: 7655974Abstract: A semiconductor device that reduces the width of an isolation region between semiconductor elements. The semiconductor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a buried layer formed between the semiconductor substrate and the epitaxial layer, a first trench formed in the epitaxial layer so as to surround the buried layer, and an insulation film formed in the first trench.Type: GrantFiled: July 27, 2007Date of Patent: February 2, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Satoru Shimada, Yoshikazu Yamaoka, Kazunori Fujita, Tomonori Tabe
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Patent number: 7646062Abstract: A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried in the semiconductor substrate further inward from the gate electrode, a wiring layer formed in the semiconductor substrate in connection with the conductor, and an insulation film arranged between the gate electrode and the conductor. The conductor is higher than the surface of the semiconductor substrate.Type: GrantFiled: June 28, 2007Date of Patent: January 12, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Yoshikazu Yamaoka, Satoru Shimada
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Publication number: 20090268031Abstract: An electric device enabling the user to visually judge the section of present and amount of a substance absorbing or reflecting ultraviolet radiation. The electric device comprises an image detecting portion (6, 66, 127, 149) for receiving ultraviolet radiation and detecting an image from the received ultraviolet radiation and a display section (2, 32, 42, 52, 62, 82, 92, 102, 126, 147, 172) for displaying ultraviolet radiation information created from the image formed by the detected ultraviolet radiation by the image detecting portion.Type: ApplicationFiled: September 13, 2006Publication date: October 29, 2009Inventors: Kazunari Honma, Mamoru Arimoto, Hitoshi Hirano, Satoru Shimada
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Publication number: 20090197378Abstract: A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the semiconductor substrate by implanting the impurity through the defect suppression film, a third step of removing the defect suppression film and a fourth step of forming an interface state suppression film suppressing increase in an interface state density of the active region on the active region.Type: ApplicationFiled: January 30, 2009Publication date: August 6, 2009Applicants: Sanyo Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Satoru Shimada, Yasuhiro Takeda, Seiji Otake
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Patent number: 7439578Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.Type: GrantFiled: December 28, 2006Date of Patent: October 21, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Yasuhiro Takeda, Mitsuaki Morigami, Satoru Shimada, Kazuhiro Yoshitake, Shuichi Kikuchi, Seiji Otake, Toshiyuki Ohkoda
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Publication number: 20080185638Abstract: A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.Type: ApplicationFiled: December 27, 2007Publication date: August 7, 2008Applicant: Sanyo Electric Co.,Ltd.Inventors: Yoshikazu YAMAOKA, Satoru Shimada, Kazunori Fujita, Kazuhiro Sasada
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Publication number: 20080173924Abstract: A semiconductor device that reduces the interval between gate electrodes. The semiconductor device includes a semiconductor substrate, a plurality of gate electrodes buried in the semiconductor substrate, a plurality of first insulation layers arranged respectively on the plurality of gate electrodes, a conductive layer formed on the surface of the semiconductor substrate near the plurality of gate electrodes and the plurality of first insulation layers, and a conductor layer arranged on at least the conductive layer.Type: ApplicationFiled: July 30, 2007Publication date: July 24, 2008Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tomonori TABE, Satoru Shimada, Kazunori Fujita, Yoshikazu Yamaoka
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Publication number: 20080023787Abstract: A semiconductor device that reduces the width of an isolation region between semiconductor elements. The semiconductor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a buried layer formed between the semiconductor substrate and the epitaxial layer, a first trench formed in the epitaxial layer so as to surround the buried layer, and an insulation film formed in the first trench.Type: ApplicationFiled: July 27, 2007Publication date: January 31, 2008Applicant: SANYO ELECTRIC CO., LTD.Inventors: Satoru SHIMADA, Yoshikazu YAMAOKA, Kazunori FUJITA, Tomonori TABE
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Publication number: 20080001214Abstract: A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried in the semiconductor substrate further inward from the gate electrode, a wiring layer formed in the semiconductor substrate in connection with the conductor, and an insulation film arranged between the gate electrode and the conductor. The conductor is higher than the surface of the semiconductor substrate.Type: ApplicationFiled: June 28, 2007Publication date: January 3, 2008Applicant: SANYO ELECTRIC CO., LTD.Inventors: Yoshikazu Yamaoka, Satoru Shimada
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Publication number: 20070292061Abstract: A device for rotating body capable of reducing fluid resistance loss by making use of the conventional bearing technology. The device is provided with a rotating body held rotatably; and one or more covering rotating bodies are installed on the outer side of the rotating body and held rotatably and coaxially with the rotating body. Bearing means are provided between the rotating body and the covering rotating body adjacent thereto or between the covering rotating bodies adjacent to each other, and bearings for the respective covering rotating bodies are disposed in series in relation to bearings for the rotating body. In addition, by filling up the interior of a case with hydrogen gas or helium gas, lower in density than air, windage loss can be further reduced.Type: ApplicationFiled: August 22, 2007Publication date: December 20, 2007Applicants: Tamura Electric Works, Ltd., Yukigaya Institute Co., Ltd.Inventors: Satoru Shimada, Shigeru Suzuki, Koichi Aoyama, Sumiko Seki, Takahiko Ito
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Publication number: 20070215872Abstract: The present invention encompasses an organic field-effect transistor comprising an n-type organic semiconductor formed of a fullerene derivative having a fluorinated alkyl group which is expressed by the following chemical formula (wherein at least any one of R1, R2 and R3 is a perfluoro alkyl group or a partially-fluorinated semifluoro alkyl group each having a carbon number of 1 to 20), and a field-effect transistor production method comprising forming an organic semiconductor layer using the fullerene derivative by a solution process, and subjecting the organic semiconductor layer to a heat treatment in an atmosphere containing nitrogen or argon or in vacuum to provide enhanced characteristics to the organic semiconductor layer. The present invention makes it possible to form an organic semiconductor layer by a solution process and provide an organic field-effect transistor excellent in electron mobility and on-off ratio and capable of operating even in an ambient air atmosphere.Type: ApplicationFiled: March 20, 2007Publication date: September 20, 2007Inventors: Masayuki Chikamatsu, Atsushi Itakura, Tatsumi Kimura, Satoru Shimada, Yuji Yoshida, Reiko Azumi, Kiyoshi Yase
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Publication number: 20070166925Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.Type: ApplicationFiled: December 28, 2006Publication date: July 19, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Yasuhiro Takeda, Mitsuaki Morigami, Satoru Shimada, Kazuhiro Yoshitake, Shuichi Kikuchi, Seiji Otake, Toshiyuki Ohkoda
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Patent number: 7231763Abstract: A hydraulic system 10 of the present invention has a hydraulic pump driven by a driving source 14, a hydraulic pump motor 52 driven by an operating oil discharged from the hydraulic pump and flowing in an oil path 50, an inertial body 60 connected to a rotary shaft of the hydraulic pump motor, an oil path 62 connected between an outlet port of the hydraulic pump motor and a load 22, an unloading oil path 64 branched from the oil path 62, and an on-off valve 68 inserted in the unloading oil path. In this configuration, as the on-off valve is opened and closed, a high pressure is generated in the oil path 62 by making use of kinetic energy of the inertial body. The inertial body is driven by hydraulic power and the inertial body is separated from the driving source, which also provides an effect of increasing degrees of freedom for an instrument layout.Type: GrantFiled: October 17, 2003Date of Patent: June 19, 2007Assignees: Saxa, Inc., Yukigaya Institute Co., Ltd.Inventors: Shigeru Suzuki, Satoru Shimada, Takahiro Yamano, Sumiko Seki, Takahiko Itoh
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Publication number: 20070131985Abstract: A semiconductor device and a method for manufacturing the same are provided, in which the work function of a gate electrode being in contact with a gate insulating film can be efficiently adjusted while depletion of the gate electrode is suppressed. An SOI substrate is composed of a p-type silicon substrate, a buried oxide film, and a single crystal silicon layer. Furthermore, source and drain regions are provided in the single crystal silicon layer. In the single crystal silicon layer, the surface between the source and drain regions serves as a channel layer. A gate insulating film is formed on the single crystal silicon layer (the channel layer). On the gate insulating film is provided a polysilicon gate electrode composed of metal particles of TiN and a polysilicon film. The metal particles of TiN include particles being in contact with the gate insulating film and particles being out of contact with this film.Type: ApplicationFiled: November 29, 2006Publication date: June 14, 2007Inventors: Kazunori Fujita, Yoshikazu Yamaoka, Satoru Shimada, Hideki Mizuhara, Yasunori Inoue
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Publication number: 20070120203Abstract: A semiconductor device includes a semiconductor substrate on which a source region and a drain region are formed, an insulating film formed on the semiconductor substrate and interposed between the source region and the drain region, a gate electrode formed on the insulating film, metal-bearing particles formed on the interface between the insulation film and the gate electrode, and an insulator which has been changed from a part of metal-bearing particles protruding from an edge of the interface.Type: ApplicationFiled: November 27, 2006Publication date: May 31, 2007Inventors: Yoshikazu Yamaoka, Kazunori Fujita, Satoru Shimada, Hideki Mizuhara, Yasunori Inoue
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Publication number: 20060117745Abstract: A hydraulic system 10 of the present invention has a hydraulic pump driven by a driving source 14, a hydraulic pump motor 52 driven by an operating oil discharged from the hydraulic pump and flowing in an oil path 50, an inertial body 60 connected to a rotary shaft of the hydraulic pump motor, an oil path 62 connected between an outlet port of the hydraulic pump motor and a load 22, an unloading oil path 64 branched from the oil path 62, and an on-off valve 68 inserted in the unloading oil path. In this configuration, as the on-off valve is opened and closed, a high pressure is generated in the oil path 62 by making use of kinetic energy of the inertial body. The inertial body is driven by hydraulic power and the inertial body is separated from the driving source, which also provides an effect of increasing degrees of freedom for an instrument layout.Type: ApplicationFiled: October 17, 2003Publication date: June 8, 2006Inventors: Shigeru Suzuki, Satoru Shimada, Takahiro Yamano, Sumiko Seki, Takahiko Itoh
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Patent number: 7045434Abstract: A method for manufacturing a semiconductor substrate including a mask aligning trench. The method includes forming the mask aligning trench and an element partitioning trench. The element partitioning and mask aligning trenches are filled with insulation. The insulation in the element partitioning trench is masked and the insulation in the mask aligning trench is etched. As a result, a residue of the insulation in the mask aligning trench is below the upper edge of the mask aligning trench. The mask aligning trench is easily detected. Thus, positioning a patterning mask on the substrate can be performed accurately.Type: GrantFiled: July 20, 2001Date of Patent: May 16, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Masaki Hirase, Satoru Shimada