Patents by Inventor Satoru Taji

Satoru Taji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6075267
    Abstract: A non-volatile semiconductor memory device includes a substrate and a continuously formed drain diffusion layer and a continuously formed source diffusion layer which are alternately arranged within the substrate. Floating gates are disposed via a tunnel insulating film on the substrate so that they are adjacent to the drain diffusion layer. The floating gates are opposed to each other with the drain diffusion layer therebetween, and spaced away from the source diffusion layer. A control gate extends in a direction orthogonal with a direction in which the source and drain diffusion layers extend, the control gate being formed on the floating gates and the substrate via an insulating film. A select channel is provided between the floating gate closest to the source diffusion layer and the source diffusion layer. A thick insulating film is provided between the drain diffusion layer and the control gate between the floating gates which are opposed to each other with the drain diffusion layer therebetween.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: June 13, 2000
    Assignee: Ricoh Company, Ltd.
    Inventors: Satoru Taji, Hiroaki Nakanishi
  • Patent number: 5966325
    Abstract: A memory cell of a memory device is constructed such that a source diffusion layer is divided into blocks each containing 16 word lines, and such that a drain diffusion layer is not divided. Each segment of the source diffusion layer is connected to a metal bit line via a block selection MOS transistor. The metal bit line is formed on an insulating film provided on the source diffusion layer so as to be parallel with the source diffusion layer. The block selection MOS transistor is connected to the metal bit line via a contact hole. A gate electrode of the block selection MOS transistor is formed of a polysilicon film for providing a selection gate used to form a word line of the memory cell. A source diffusion layer and a drain diffusion layer of the block selection MOS transistor are formed of the same material as the source diffusion layer of the memory cell and the drain diffusion layer of the memory cell.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: October 12, 1999
    Assignee: Ricoh Company, Ltd.
    Inventors: Hiroaki Nakanishi, Satoru Taji
  • Patent number: 5311463
    Abstract: A semiconductor memory device has a diffusive region for a source formed in the shape of a band on a substrate; a diffusive region for a drain formed in the shape of a band in parallel with the diffusive region for a source and alternated with this diffusive region for a source; a first word line layer formed such that the first word line layer crosses the diffusive regions for a source and a drain; and a second word line layer formed in parallel with the first word line layer. The semiconductor memory device further has a channel region including an a-region on a substrate surface located on the lower side of a flat portion within a region prescribed between the diffusive regions for a source and a drain; and two b-regions on the substrate surface arranged on both sides of the a-region and located on the lower sides of first and second side wall portions.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: May 10, 1994
    Assignee: Ricoh Company, Ltd.
    Inventor: Satoru Taji
  • Patent number: 4810666
    Abstract: A method for manufacturing a MOSIC includes a step of forming a protective film of silicon nitride, which covers the top and side walls of a gate electrode structure including a doped polysilicon, a step of forming an interlayer insulating film and a step of forming a contact pattern in the interlayer insulating film immediately adjacent to a portion of the protective film in a self-aligned fashion with respect to the gate electrode structure. The presence of the protective film which covers the top and side walls of the doped polysilicon, which defines a gate electrode of a MOSFET, allows forming a pair of associated contact holes for drain and source regions in a self-aligned fashion, which contributes for higher integration.
    Type: Grant
    Filed: July 2, 1985
    Date of Patent: March 7, 1989
    Assignee: Ricoh Company, Ltd.
    Inventor: Satoru Taji
  • Patent number: 4634494
    Abstract: The etch rate of phosphosilicate glass becomes lowered as boron ions are implanted therein. In accordance with the principle of the present invention, boron ions are implanted into a phosphosilicate glass film selectively in location or concentration and the thus boron-implanted phosphosilicate glass film is etched by an etchant, for example buffered hydrofluoric acid solution, to etch an intended portion of the phosphosilcate glass film preferentially thereby defining a hole, such as a contact hole, or substantially flat surface.
    Type: Grant
    Filed: July 29, 1985
    Date of Patent: January 6, 1987
    Assignee: Ricoh Company, Ltd.
    Inventors: Satoru Taji, Norio Yoshida, Tetsuo Hikawa