Abstract: A wafer test apparatus, comprises: a storage unit that stores a first test program including a plurality of first operation test programs and a second test program including a plurality of second operation test programs; and a calculation unit that executes the first test program on at least one of wafers in a lot and outputs accumulated information about a defective memory cell(s) included in the wafer to the outside thereof when each operation test of the plurality of first operation tests is completed, and executes the second test program on remaining wafers in the lot and outputs accumulated information about a defective memory cell(s) included in the wafer to the outside thereof when all the operation tests in the plurality of second operation tests are completed.