Patents by Inventor Satoru TOKUDA
Satoru TOKUDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088238Abstract: A semiconductor device includes a trench formed in an n-type semiconductor substrate, a p-type body region, an n-type source region, a field plate electrode formed at a lower portion of the trench, and a gate electrode formed at an upper portion of the trench. A gate potential is to be supplied to the gate electrode, a source potential is to be supplied to the source region and the body region, and a drain potential is to be supplied to the semiconductor substrate. A potential larger than the source potential and smaller than the drain potential is to be supplied to the field plate electrode.Type: ApplicationFiled: June 7, 2023Publication date: March 14, 2024Inventor: Satoru TOKUDA
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Publication number: 20230231011Abstract: A semiconductor device that achieves both miniaturization and high breakdown voltage is disclosed. The semiconductor device has a gate electrode G1 formed in a trench TR extending in Y direction and a plurality of column regions PC including column regions PC1 to PC3 formed in a drift region ND. The column regions PC1, PC2 and PC3 are provided in a staggered manner to sandwich the trench TR. An angle ?1 formed by a line connecting the centers of the column regions PC1 and PC2 and a line connecting the centers of the column regions PC1 and PC3 is 60 degrees or more and 90 degrees or less.Type: ApplicationFiled: March 24, 2023Publication date: July 20, 2023Inventor: Satoru Tokuda
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Publication number: 20230118274Abstract: A semiconductor device includes a cell region in which a plurality of unit cells are formed, and an outer peripheral region surrounding the cell region in plan view. Each of the plurality of unit cells includes a semiconductor substrate having a drift region, a body region, a source region, a pair of first column regions, and a gate electrode formed in a trench with a gate insulating film interposed therebetween. A well region is formed on a surface of the drift region in the outer peripheral region. A second column region is formed in the drift region below the well region and extends in Y and X directions so as to surround the cell region. The well region is connected to the body region, and the second column region is connected to the well region.Type: ApplicationFiled: August 12, 2022Publication date: April 20, 2023Inventors: Yuta NABUCHI, Katsumi EIKYU, Atsushi SAKAI, Akihiro SHIMOMURA, Satoru TOKUDA
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Publication number: 20230111142Abstract: A semiconductor device includes a plurality of unit cells. Each of the plurality of unit cells has a pair of column regions, a pair of trenches formed between the pair of column regions in the X direction, and a pair of gate electrodes formed in the pair of trenches via a gate insulating film, respectively. The two unit cells adjacent in the X direction share one column region of the pair of column regions and are arranged to be symmetrical about the shared column region. Here, a distance between the two trenches, which are adjacent with the one column region interposed therebetween, of the trenches in the two adjacent unit cells is different from a distance between the pair of trenches in the one unit cell.Type: ApplicationFiled: August 11, 2022Publication date: April 13, 2023Inventors: Katsumi EIKYU, Yuta NABUCHI, Atsushi SAKAI, Akihiro SHIMOMURA, Satoru TOKUDA
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Patent number: 11362207Abstract: A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.Type: GrantFiled: November 11, 2020Date of Patent: June 14, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi Sakai, Satoru Tokuda, Ryuuji Umemoto, Katsumi Eikyu, Hiroshi Yanagigawa
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Publication number: 20210159331Abstract: A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.Type: ApplicationFiled: November 11, 2020Publication date: May 27, 2021Inventors: Atsushi SAKAI, Satoru TOKUDA, Ryuuji UMEMOTO, Katsumi EIKYU, Hiroshi YANAGIGAWA
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Publication number: 20200258979Abstract: A semiconductor device that achieves both miniaturization and high breakdown voltage is disclosed. The semiconductor device has a gate electrode G1 formed in a trench TR extending in Y direction and a plurality of column regions PC including column regions PC1 to PC3 formed in a drift region ND. The column regions PC1, PC2 and PC3 are provided in a staggered manner to sandwich the trench TR. An angle ?1 formed by a line connecting the centers of the column regions PC1 and PC2 and a line connecting the centers of the column regions PC1 and PC3 is 60 degrees or more and 90 degrees or less.Type: ApplicationFiled: February 5, 2020Publication date: August 13, 2020Inventor: Satoru TOKUDA
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Patent number: 10600904Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; a first wiring and a second wiring disposed on the first surface; a first conductive film electrically connected to the first wiring; and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The drift region is disposed so as to surround the body region in a plan view. The first wiring has a first portion disposed so as to extend across a boundary between the drift region and the body region in a plan view, and electrically connected to the drift region. The second wiring is electrically connected to the source region. The first conductive film is insulated from and faces the second wiring.Type: GrantFiled: April 18, 2018Date of Patent: March 24, 2020Assignee: Renesas Electronics CorporationInventors: Hiroyoshi Kudou, Satoru Tokuda, Satoshi Uchiya
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Patent number: 10584894Abstract: Air-blowing from a second air outlet is effectively used. An air conditioner includes a main body unit and an auxiliary housing. The main body unit forms a first air outlet which blows out a cool or warm airflow. The auxiliary housing is attached to at least one side of the first air outlet to be freely movable, and forms a second air outlet which blows out taken-in indoor air. A control circuit blows out the indoor air from the second air outlet at a wind speed which is higher than the wind speed of cool air or warm air that is blown out of the first air outlet.Type: GrantFiled: December 27, 2013Date of Patent: March 10, 2020Assignee: FUJITSU GENERAL LIMITEDInventors: Syun Iwano, Tomofumi Kawai, Satoru Tokuda
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Publication number: 20200020799Abstract: A semiconductor device capable of reducing the influence of noise and easily securing a breakdown voltage between a source wiring and a drain wiring constituting a capacitance between a source and a drain even when shrinkage of a cell progresses, and a manufacturing method thereof are provided. The drain wiring is electrically connected to a substrate region, and the drain wiring is disposed in contact with an upper surface of an interlayer insulating layer. The source wiring is electrically connected to source regions and are disposed in contact with the upper surface of the interlayer insulating layer. A plurality of MOSFET cells are arranged side by side in a X-direction. The drain wiring and the source wiring extends in the X direction and are adjacent to each other in a Y direction crossing the X direction to form a capacitor.Type: ApplicationFiled: June 19, 2019Publication date: January 16, 2020Inventors: Yoshiaki UEDA, Satoru TOKUDA, Satoshi UCHIYA, Hiroyoshi KUDOU
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Patent number: 10224428Abstract: The present invention provides a semiconductor device that can reduce effects of noise without complicating processes or increasing chip area. The semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a drain region, a drift region, a base region, a source region, a gate electrode, an interlayer insulating film, a conductive layer electrically coupled to the drain region, a wiring line, and a contact plug electrically coupled to the source region and the wiring line. The interlayer insulating film has an intermediate interlayer insulating film. The intermediate interlayer insulating film is arranged between the conductive layer and the contact plug. The intermediate interlayer insulating film is a thermal oxide film of a material that forms the conductive layer.Type: GrantFiled: October 3, 2017Date of Patent: March 5, 2019Assignee: Renesas Electronics CorporationInventor: Satoru Tokuda
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Publication number: 20180366575Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; a first wiring and a second wiring disposed on the first surface; a first conductive film electrically connected to the first wiring; and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The drift region is disposed so as to surround the body region in a plan view. The first wiring has a first portion disposed so as to extend across a boundary between the drift region and the body region in a plan view, and electrically connected to the drift region. The second wiring is electrically connected to the source region. The first conductive film is insulated from and faces the second wiring.Type: ApplicationFiled: April 18, 2018Publication date: December 20, 2018Inventors: Hiroyoshi KUDOU, Satoru TOKUDA, Satoshi UCHIYA
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Publication number: 20180138311Abstract: The present invention provides a semiconductor device that can reduce effects of noise without complicating processes or increasing chip area. The semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a drain region, a drift region, a base region, a source region, a gate electrode, an interlayer insulating film, a conductive layer electrically coupled to the drain region, a wiring line, and a contact plug electrically coupled to the source region and the wiring line. The interlayer insulating film has an intermediate interlayer insulating film. The intermediate interlayer insulating film is arranged between the conductive layer and the contact plug. The intermediate interlayer insulating film is a thermal oxide film of a material that forms the conductive layer.Type: ApplicationFiled: October 3, 2017Publication date: May 17, 2018Applicant: Renesas Electronics CorporationInventor: Satoru TOKUDA
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Publication number: 20160043214Abstract: A first lower insulating film (LIL1) is formed on the bottom surface and a lower portion of the side surface of a first concave portion (gate trench) and is thicker than a gate insulating film (GIF). An upper end of LIL1 is connected to a lower end of the GIF. A second lower insulating film is formed on the bottom surface and a lower portion of the side surface of a second concave portion (termination trench). An upper insulating film (UIF) is formed at an upper portion of the side surface of the second concave portion and a lower end is connected to an upper end of LIL2. The depth of the second concave portion is ?90% and ?110% of the depth of the first concave portion. The thickness of LIL2 is ?95% and ?105% of the thickness of LIL1. The UIF is thicker than the GIF.Type: ApplicationFiled: October 21, 2015Publication date: February 11, 2016Inventor: Satoru TOKUDA
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Publication number: 20150354850Abstract: Air-blowing from a second air outlet is effectively used. An air conditioner includes a main body unit and an auxiliary housing. The main body unit forms a first air outlet which blows out a cool or warm airflow. The auxiliary housing is attached to at least one side of the first air outlet to be freely movable, and forms a second air outlet which blows out taken-in indoor air. A control circuit blows out the indoor air from the second air outlet at a wind speed which is higher than the wind speed of cool air or warm air that is blown out of the first air outlet.Type: ApplicationFiled: December 27, 2013Publication date: December 10, 2015Inventors: Syun IWANO, Tomofumi KAWAI, Satoru TOKUDA
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Patent number: 9196720Abstract: A first lower insulating film (LIL1) is formed on the bottom surface and a lower portion of the side surface of a first concave portion (gate trench) and is thicker than a gate insulating film (GIF). An upper end of LIL1 is connected to a lower end of the GIF. A second lower insulating film is formed on the bottom surface and a lower portion of the side surface of a second concave portion (termination trench). An upper insulating film (UIF) is formed at an upper portion of the side surface of the second concave portion and a lower end is connected to an upper end of LIL2. The depth of the second concave portion is ?90% and ?110% of the depth of the first concave portion. The thickness of LIL2 is ?95% and ?105% of the thickness of LIL1. The UIF is thicker than the GIF.Type: GrantFiled: January 10, 2014Date of Patent: November 24, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Satoru Tokuda
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Publication number: 20140210000Abstract: A first lower insulating film (LIL1) is formed on the bottom surface and a lower portion of the side surface of a first concave portion (gate trench) and is thicker than a gate insulating film (GIF). An upper end of LIL1 is connected to a lower end of the GIF. A second lower insulating film is formed on the bottom surface and a lower portion of the side surface of a second concave portion (termination trench). An upper insulating film (UIF) is formed at an upper portion of the side surface of the second concave portion and a lower end is connected to an upper end of LIL2. The depth of the second concave portion is ?90% and ?110% of the depth of the first concave portion. The thickness of LIL2 is ?95% and ?105% of the thickness of LIL1. The UIF is thicker than the GIF.Type: ApplicationFiled: January 10, 2014Publication date: July 31, 2014Applicant: Renesas Electronics CorporationInventor: Satoru TOKUDA
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Publication number: 20100193864Abstract: A semiconductor device includes a plurality of first gate electrodes that are arranged above a semiconductor substrate in a first direction, and a plurality of second gate electrodes that are arranged above the semiconductor substrate in a second direction. The semiconductor device further includes a first gate lead-out electrode to which the first gate electrodes are connected, a second gate lead-out electrode to which the second gate electrodes are connected, and a third gate lead-out electrode to which the first gate lead-out electrode and the second gate lead-out electrode are connected. In the semiconductor device according to the present invention, a punched pattern is formed in the third gate lead-out electrode.Type: ApplicationFiled: January 14, 2010Publication date: August 5, 2010Inventor: Satoru TOKUDA
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Publication number: 20080093736Abstract: A semiconductor die has a top surface and a bottom surface. A source contact, a gate contact and a gate finger are formed on the top surface. The source contact has a slit and the gate finger is disposed in the slit of the source contact. A drain contact is formed on the bottom surface. An insulation layer is formed on the top surface to cover the gate finger. A semiconductor device includes the semiconductor die and an electrically conductive sheet attached to the source contact with a conductive paste. The electrically conductive sheet has a concave portion disposed above the gate finger. An air gap is formed between the concave portion and the insulation layer. By including the air gap, the stress that occurs between the electrically conductive sheet and the insulation layer can be reduced, thus an occurrence of a crack in the insulation layer can be prevented.Type: ApplicationFiled: October 19, 2007Publication date: April 24, 2008Applicant: NEC ELECTRONICS CORPORATIONInventor: Satoru TOKUDA