Patents by Inventor Satoru Utsugi

Satoru Utsugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955559
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 9, 2024
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Yoshiaki Matsushima, Shigeru Ishida, Ryohei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto, Satoshi Michinaka
  • Publication number: 20210391475
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Inventors: YOSHIAKI MATSUSHIMA, SHIGERU ISHIDA, RYOHEI TAKAKURA, SATORU UTSUGI, NOBUTAKE NODERA, TAKAO MATSUMOTO, SATOSHI MICHINAKA
  • Publication number: 20190140102
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Application
    Filed: April 25, 2016
    Publication date: May 9, 2019
    Applicant: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: YOSHIAKI MATSUSHIMA, SHIGERU ISHIDA, RYOHEI TAKAKURA, SATORU UTSUGI, NOBUTAKE NODERA, TAKAO MATSUMOTO, SATOSHI MICHINAKA
  • Patent number: 10263121
    Abstract: Provided are a thin film transistor having properties properly adjusted by adjusting crystallinity of a polycrystalline silicon, and a method of manufacturing the same. The silicon layer functioning as a channel layer of a TFT comprises an amorphous part, a first polycrystalline part and a second polycrystalline part. The first and second polycrystalline parts are formed by irradiating the silicon layer with laser beams (energy beams) through the mask comprising the shielding part for shielding the energy beams, the first transmission part for transmitting the energy beams and the second transmission part for transmitting the energy beams at a transmittance lower than that of the first transmission part. By the presence of the second polycrystalline part, properties of the TFT such as an electron mobility are properly adjusted. Further, properties of the TFT can be adjusted easily by adjusting the configuration of the mask.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 16, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Yoshiaki Matsushima, Shigeru Ishida, Ryouhei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10256350
    Abstract: A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer including an amorphous silicon, irradiating a region of the first silicon layer from a part or the whole of a predetermined region of the first silicon layer to an outside of the predetermined region with an energy beam so as to convert a portion of the first silicon layer into a polycrystalline silicon, a first etching step for etching the first silicon layer while leaving the predetermined region, forming a second silicon layer including an amorphous silicon so as to cover the predetermined region, a second etching step for etching the second silicon layer covering the predetermined region while leaving a part of the second silicon layer, the part larger than the predetermined region, and forming a source electrode and a drain electrode.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 9, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Satoru Utsugi, Shigeru Ishida, Ryouhei Takakura, Yoshiaki Matsushima, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10115746
    Abstract: Provided is a manufacturing method for an active matrix substrate, capable of providing a hole for alignment at an interlayer dielectric film without possible etching of a substrate surface and abnormal electric discharge and of allowing the position of a formed film to be easily corrected to be aligned with the position of the film of the lowest layer, with high overlaying precision. Also provided are the active matrix substrate and a display apparatus comprising the active matrix substrate. An interlayer dielectric film 14 of the active matrix substrate is formed using an SOG material with photosensitivity, and an adjustment hole 14b for adjustment of the patterns of a gate insulation film 15, a first semiconductor film 16, a second semiconductor film 17 and a source metal that are formed on the upper side of a substrate 10 and the interlayer dielectric film 14 is formed. The position of each film is adjusted while viewing an edge of the gate wiring 11 through the adjustment hole 14b.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: October 30, 2018
    Assignee: Sakai Display Products Corporation
    Inventors: Masahiro Kato, Satoru Utsugi
  • Publication number: 20180212065
    Abstract: Provided are a thin film transistor having properties properly adjusted by adjusting crystallinity of a polycrystalline silicon, and a method of manufacturing the same. The silicon layer functioning as a channel layer of a TFT comprises an amorphous part, a first polycrystalline part and a second polycrystalline part. The first and second polycrystalline parts are formed by irradiating the silicon layer with laser beams (energy beams) through the mask comprising the shielding part for shielding the energy beams, the first transmission part for transmitting the energy beams and the second transmission part for transmitting the energy beams at a transmittance lower than that of the first transmission part. By the presence of the second polycrystalline part, properties of the TFT such as an electron mobility are properly adjusted. Further, properties of the TFT can be adjusted easily by adjusting the configuration of the mask.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 26, 2018
    Inventors: Yoshiaki Matsushima, Shigeru Ishida, Ryouhei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10031361
    Abstract: A liquid crystal layer is disposed on a second glass substrate side between a first glass substrate and a second glass substrate, a first insulating film and a second insulating film are formed in this order on a surface of the first glass substrate that is disposed on the liquid crystal layer side, the outer edge portion of the liquid crystal layer is surrounded by a sealing material, and a slit is formed in a part or the whole of the peripheral edge portion of the second insulating film disposed on a further inner side than a position at which the second insulating film overlaps the sealing material. In addition, a slit formed in a peripheral edge portion of the first insulating film that corresponds to the sealing material is filled with a gate insulating film having a higher barrier property for gas and/or liquid than the first insulating film.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: July 24, 2018
    Assignee: Sakai Display Products Corporation
    Inventors: Ryo Murata, Shinji Koiwa, Yoshiaki Matsushima, Satoru Utsugi
  • Publication number: 20180204957
    Abstract: A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer including an amorphous silicon, irradiating a region of the first silicon layer from a part or the whole of a predetermined region of the first silicon layer to an outside of the predetermined region with an energy beam so as to convert a portion of the first silicon layer into a polycrystalline silicon, a first etching step for etching the first silicon layer while leaving the predetermined region, forming a second silicon layer including an amorphous silicon so as to cover the predetermined region, a second etching step for etching the second silicon layer covering the predetermined region while leaving a part of the second silicon layer, the part larger than the predetermined region, and forming a source electrode and a drain electrode.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 19, 2018
    Inventors: Satoru Utsugi, Shigeru Ishida, Ryouhei Takakura, Yoshiaki Matsushima, Nobutake Nodera, Takao Matsumoto
  • Publication number: 20160336357
    Abstract: Provided is a manufacturing method for an active matrix substrate, capable of providing a hole for alignment at an interlayer dielectric film without possible etching of a substrate surface and abnormal electric discharge and of allowing the position of a formed film to be easily corrected to be aligned with the position of the film of the lowest layer, with high overlaying precision. Also provided are the active matrix substrate and a display apparatus comprising the active matrix substrate. An interlayer dielectric film 14 of the active matrix substrate is formed using an SOG material with photosensitivity, and an adjustment hole 14b for adjustment of the patterns of a gate insulation film 15, a first semiconductor film 16, a second semiconductor film 17 and a source metal that are formed on the upper side of a substrate 10 and the interlayer dielectric film 14 is formed. The position of each film is adjusted while viewing an edge of the gate wiring 11 through the adjustment hole 14b.
    Type: Application
    Filed: January 8, 2014
    Publication date: November 17, 2016
    Applicant: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Masahiro Kato, Satoru Utsugi
  • Publication number: 20160070133
    Abstract: A liquid crystal layer is disposed on a second glass substrate side between a first glass substrate and a second glass substrate, a first insulating film and a second insulating film are formed in this order on a surface of the first glass substrate that is disposed on the liquid crystal layer side, the outer edge portion of the liquid crystal layer is surrounded by a sealing material, and a slit is formed in a part or the whole of the peripheral edge portion of the second insulating film disposed on a further inner side than a position at which the second insulating film overlaps the sealing material. In addition, a slit formed in a peripheral edge portion of the first insulating film that corresponds to the sealing material is filled with a gate insulating film having a higher barrier property for gas and/or liquid than the first insulating film.
    Type: Application
    Filed: May 23, 2014
    Publication date: March 10, 2016
    Inventors: Ryo Murata, Shinji Koiwa, Yoshiaki Matsushima, Satoru Utsugi