Patents by Inventor Satoru Yamagata

Satoru Yamagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7560775
    Abstract: In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D? of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1?(B/D)2)0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: July 14, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshiji Takamura, Noboru Takeuchi, Satoru Yamagata
  • Patent number: 7542326
    Abstract: A semiconductor memory device comprises an array of memory cells each comprising a variable resistance element and a cell access transistor, and a voltage supplying means for applying the first voltage between the bit and source lines connected to the selected memory cell, the third voltage to the word line to apply the first write voltage between the two ports of the variable resistance element for shifting the resistance from the first state to the second state, and the second voltage opposite in polarity to the first voltage between the bit and source lines, the third voltage to the word line to apply the second write voltage opposite in polarity to and different in the absolute value from the first write voltage between the two ports for shifting the resistance from the second state to the first state, the voltage supplying means comprising an n-channel MOSFET and a p-channel MOSFET.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: June 2, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Yoshimura, Shinichi Sato, Satoru Yamagata, Shinji Horii
  • Patent number: 7511986
    Abstract: The possibility of the loss of information stored in a memory cell which is caused by repeating the reading action on the same memory cell comprising a variable resistance element and a select transistor can significantly be reduced. A voltage applying circuit for selecting one or more of the memory cells from a memory cell array and applying voltages to the word lines, bit lines, and source lines for programming, erasing, and reading information applies a voltage between the bit line and the source line connected to the selected memory cell so that the voltage applied between the two ports of the variable resistance element in the selected memory cell during the reading action is equal in the polarity to one of the voltages applied between the two ports of the variable resistance element for the programming action and the erasing action respectively whichever is greater in the absolute value.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: March 31, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinji Horii, Satoru Yamagata
  • Patent number: 7511985
    Abstract: A semiconductor memory device comprises a array of memory cells arranged in a matrix, each memory cell connected to one end of a variable resistor element where the electric resistance is shifted from the first state to the second state by applying the first writing voltage and from the second state to the first state by applying the second writing voltage, and the source or drain of the selecting transistor. The second writing time for the second writing action of shifting the electric resistance of the variable resistor element from the second state to the first state is longer than the first writing time of shifting the same reversely. The second number of the memory cells subjected to the second writing action at once is greater than the first memory cell number subjected to the first writing action at once, and at least the second number is two or more.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: March 31, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinji Horii, Shinichi Sato, Satoru Yamagata
  • Publication number: 20080049487
    Abstract: A semiconductor memory device comprises an array of memory cells each comprising a variable resistance element and a cell access transistor, and a voltage supplying means for applying the first voltage between the bit and source lines connected to the selected memory cell, the third voltage to the word line to apply the first write voltage between the two ports of the variable resistance element for shifting the resistance from the first state to the second state, and the second voltage opposite in polarity to the first voltage between the bit and source lines, the third voltage to the word line to apply the second write voltage opposite in polarity to and different in the absolute value from the first write voltage between the two ports for shifting the resistance from the second state to the first state, the voltage supplying means comprising an n-channel MOSFET and a p-channel MOSFET.
    Type: Application
    Filed: August 13, 2007
    Publication date: February 28, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Satoshi Yoshimura, Shinichi Sato, Satoru Yamagata, Shinji Horii
  • Publication number: 20080025070
    Abstract: The possibility of the loss of information stored in a memory cell which is caused by repeating the reading action on the same memory cell comprising a variable resistance element and a select transistor can significantly be reduced. A voltage applying circuit for selecting one or more of the memory cells from a memory cell array and applying voltages to the word lines, bit lines, and source lines for programming, erasing, and reading information applies a voltage between the bit line and the source line connected to the selected memory cell so that the voltage applied between the two ports of the variable resistance element in the selected memory cell during the reading action is equal in the polarity to one of the voltages applied between the two ports of the variable resistance element for the programming action and the erasing action respectively whichever is greater in the absolute value.
    Type: Application
    Filed: July 17, 2007
    Publication date: January 31, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Horii, Satoru Yamagata
  • Publication number: 20070285972
    Abstract: A semiconductor memory device comprises a array of memory cells arranged in a matrix, each memory cell connected to one end of a variable resistor element where the electric resistance is shifted from the first state to the second state by applying the first writing voltage and from the second state to the first state by applying the second writing voltage, and the source or drain of the selecting transistor. The second writing time for the second writing action of shifting the electric resistance of the variable resistor element from the second state to the first state is longer than the first writing time of shifting the same reversely. The second number of the memory cells subjected to the second writing action at once is greater than the first memory cell number subjected to the first writing action at once, and at least the second number is two or more.
    Type: Application
    Filed: April 17, 2007
    Publication date: December 13, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Horii, Shinichi Sato, Satoru Yamagata
  • Patent number: 7276407
    Abstract: A method for fabricating a semiconductor device including on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second and third MOS transistors sharing a second gate insulating film smaller in thickness than the first gate insulating film, the third MOS transistor being lower in threshold voltage than the second MOS transistor, the method includes the steps of: adjusting the threshold voltages of the first and third MOS transistors by first ion-implantation; and adjusting the threshold voltage of the second MOS transistor by second ion-implantation, the second ion-implantation being performed under implantation conditions different from those of the first ion-implantation.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: October 2, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoru Yamagata, Masayuki Hirata, Shinichi Sato
  • Publication number: 20070023792
    Abstract: In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D? of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1?(B/D)2 )0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region.
    Type: Application
    Filed: July 3, 2006
    Publication date: February 1, 2007
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshiji Takamura, Noboru Takeuchi, Satoru Yamagata
  • Publication number: 20060063316
    Abstract: A method for fabricating a semiconductor device including on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second and third MOS transistors sharing a second gate insulating film smaller in thickness than the first gate insulating film, the third MOS transistor being lower in threshold voltage than the second MOS transistor, the method includes the steps of: adjusting the threshold voltages of the first and third MOS transistors by first ion-implantation; and adjusting the threshold voltage of the second MOS transistor by second ion-implantation, the second ion-implantation being performed under implantation conditions different from those of the first ion-implantation.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 23, 2006
    Inventors: Satoru Yamagata, Masayuki Hirata, Shinichi Sato
  • Publication number: 20050141276
    Abstract: A semiconductor memory device including: a semiconductor substrate; a plurality of memory cells arranged in a matrix having columns and rows on the semiconductor substrate and each including a source, a drain and a control gate; a plurality of insulative device isolation layers positioned in a surface portion of the substrate as extending in a column direction for isolating the memory cells arranged in each row of the matrix; a plurality of word lines positioned on the substrate as extending in a row direction and each constituted by the control gates of the memory cells of the each row which are connected in series; the source and the drain of each of the memory cells of the each row being positioned in the surface portion of the substrate on opposite sides of a corresponding one of the word lines between an adjacent pair of insulative device isolation layers; and a common source line positioned on the substrate between an adjacent pair of word lines with the intervention of side wall films positioned on sid
    Type: Application
    Filed: December 23, 2004
    Publication date: June 30, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Noboru Takeuchi, Satoru Yamagata, Shinichi Sato
  • Publication number: 20040183120
    Abstract: In a method for manufacturing a memory cell of a nonvolatile semiconductor memory, a floating gate, first insulating film and control gate are successively stacked on a tunnel oxide film formed on a substrate of the nonvolatile semiconductor memory. The control gate, the first insulating film and the floating gate are patterned in stripes. Subsequently, a damaged portion of the tunnel oxide film immediately below a sidewall of the floating gate is removed by isotropic etching. A second insulating film is deposited to cover the control gate, sidewalls of the first insulating film, the floating gate and the tunnel oxide film. Thereby, a variation in threshold voltages between memory cells is suppressed.
    Type: Application
    Filed: April 1, 2004
    Publication date: September 23, 2004
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Satoru Yamagata, Masanori Yoshimi
  • Patent number: 6737344
    Abstract: In a method for manufacturing a memory cell of a nonvolatile semiconductor memory, a floating gate, first insulating film and control gate are successively stacked on a tunnel oxide film formed on a substrate of the nonvolatile semiconductor memory. The control gate, the first insulating film and the floating gate are patterned in stripes. Subsequently, a damaged portion of the tunnel oxide film immediately below a sidewall of the floating gate is removed by isotropic etching. A second insulating film is deposited to cover the control gate, sidewalls of the first insulating film, the floating gate and the tunnel oxide film. Thereby, a variation in threshold voltages between memory cells is suppressed.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: May 18, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoru Yamagata, Masanori Yoshimi
  • Publication number: 20020094638
    Abstract: In a method for manufacturing a memory cell of a nonvolatile semiconductor memory, a floating gate, first insulating film and control gate are successively stacked on a tunnel oxide film formed on a substrate of the nonvolatile semiconductor memory. The control gate, the first insulating film and the floating gate are patterned in stripes. Subsequently, a damaged portion of the tunnel oxide film immediately below a sidewall of the floating gate is removed by isotropic etching. A second insulating film is deposited to cover the control gate, sidewalls of the first insulating film, the floating gate and the tunnel oxide film. Thereby, a variation in threshold voltages between memory cells is suppressed.
    Type: Application
    Filed: November 27, 2001
    Publication date: July 18, 2002
    Inventors: Satoru Yamagata, Masanori Yoshimi
  • Patent number: 5858851
    Abstract: A titanium film and a titanium nitride film are sequentially formed on a polysilicon plug. Next, the titanium nitride film is oxidized to form an oxidized titanium nitride film. Thereafter, a lower electrode and a PZT film are formed. A diffusion barrier layer is prepared from the oxidized titanium nitride film and is oxidized before the lower electrode is formed. As a result, unlike in prior art, the diffusion barrier layer is not oxidized after the lower electrode is formed. Peel-off between the diffusion barrier layer and the lower electrode due to the oxidation is thus prevented.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: January 12, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoru Yamagata, Shigeo Onishi, Jun Kudo