Patents by Inventor Satoru Yanagida

Satoru Yanagida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process of folding a strip leadframe to superpose two leadframes in a plural semiconductor die encapsulated package
    Patent number: 5614441
    Abstract: A method of manufacturing a semiconductor device wherein, a first lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads. A second lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads as in the first lead frame portion coupled to the second lead frame portion through a coupling portion. The first and second lead frame portions are folded at the coupling portion and superposed such that the two semiconductor elements oppose each other. At this time, the plurality of inner and outer leads of the first and second lead frames are alternately and adjacently arranged. Each electrode of the semiconductor elements is connected to a corresponding inner lead. The superposed first and second lead frames are sealed with a mold resin while leaving end portions of the plurality of outer leads of the first and second lead frames.
    Type: Grant
    Filed: May 4, 1995
    Date of Patent: March 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Hosokawa, Satoru Yanagida
  • Method of manufacturing resin-sealed semiconductor device, lead frame used in this method for mounting plurality of semiconductor elements, and resin-sealed semiconductor device
    Patent number: 5543658
    Abstract: According to a method of manufacturing a semiconductor device of this invention, a first lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads. A second lead frame portion has a bed portion for mounting a semiconductor element and a plurality of inner and outer leads as in the first lead frame portion coupled to the second lead frame portion through a coupling portion. The first and second lead frame portions are folded at the coupling portion and superposed each other such that the two semiconductor elements oppose each other. At this time, the plurality of inner and outer leads of the first and second lead frames are alternately and adjacently arranged. Each electrode of the semiconductor elements is connected to a corresponding inner lead. The superposed first and second lead frames are sealed with a mold resin while leaving end portions of the plurality of outer leads of the first and second lead frames.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: August 6, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Hosokawa, Satoru Yanagida
  • Semiconductor device mounted upon an insulating adhesive with silicon dioxide and nickel chromium steel filling particles
    Patent number: 5113241
    Abstract: A semiconductor device comprises a plurality of pellets fixed on a bed by a conductive adhesive agent, an insulating substrate having a junction wiring fixed on the bed between the semiconductor pellets, and wires for connecting the pellets and insulating substrate. The insulating substrate is fixed on the bed by an insulating adhesive agent including filling material such as particles of silicon dioxide and metal particles. The surfaces of the filling material particles are coated with an oxide film.
    Type: Grant
    Filed: December 14, 1990
    Date of Patent: May 12, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoru Yanagida, Kouji Araki, Hikaru Okunoyama, Tetsunori Niimi