Patents by Inventor Satoshi Ae

Satoshi Ae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10020637
    Abstract: To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (AWG) comprised of InP is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5° to 1.0° in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type InP is formed over the AWG with a V/III ratio of 2000 or more. Thereby, it is possible to obtain excellent multiple quantum wells (MQWs) by reducing a film thickness variation of the AWG. Moreover, the cover layer having side faces where a (0-11) plane almost perpendicular to a substrate surface mainly appears can be formed. A sectional shape of a lamination part of the cover layer and the AWG becomes an approximately rectangular shape. Therefore, an electrification region can be enlarged and it is possible to reduce a resistance of the semiconductor device.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: July 10, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Ae, Shoutarou Kitamura, Tetsuro Okuda, Suguru Kato, Isao Watanabe
  • Publication number: 20170271848
    Abstract: To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (AWG) comprised of InP is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5° to 1.0° in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type InP is formed over the AWG with a V/III ratio of 2000 or more. Thereby, it is possible to obtain excellent multiple quantum wells (MQWs) by reducing a film thickness variation of the AWG. Moreover, the cover layer having side faces where a (0-11) plane almost perpendicular to a substrate surface mainly appears can be formed. A sectional shape of a lamination part of the cover layer and the AWG becomes an approximately rectangular shape. Therefore, an electrification region can be enlarged and it is possible to reduce a resistance of the semiconductor device.
    Type: Application
    Filed: June 1, 2017
    Publication date: September 21, 2017
    Inventors: Satoshi AE, Shoutarou KITAMURA, Tetsuro OKUDA, Suguru KATO, Isao WATANABE
  • Patent number: 9698569
    Abstract: To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (AWG) comprised of InP is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5° to 1.0° in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type InP is formed over the AWG with a V/III ratio of 2000 or more. Thereby, it is possible to obtain excellent multiple quantum wells (MQWs) by reducing a film thickness variation of the AWG. Moreover, the cover layer having side faces where a (0-11) plane almost perpendicular to a substrate surface mainly appears can be formed. A sectional shape of a lamination part of the cover layer and the AWG becomes an approximately rectangular shape. Therefore, an electrification region can be enlarged and it is possible to reduce a resistance of the semiconductor device.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: July 4, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Ae, Shoutarou Kitamura, Tetsuro Okuda, Suguru Kato, Isao Watanabe
  • Publication number: 20150085888
    Abstract: To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (AWG) comprised of InP is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5° to 1.0° in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type InP is formed over the AWG with a V/III ratio of 2000 or more. Thereby, it is possible to obtain excellent multiple quantum wells (MQWs) by reducing a film thickness variation of the AWG. Moreover, the cover layer having side faces where a (0-11) plane almost perpendicular to a substrate surface mainly appears can be formed. A sectional shape of a lamination part of the cover layer and the AWG becomes an approximately rectangular shape. Therefore, an electrification region can be enlarged and it is possible to reduce a resistance of the semiconductor device.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 26, 2015
    Inventors: Satoshi AE, Shoutarou KITAMURA, Tetsuro OKUDA, Suguru KATO, Isao WATANABE
  • Patent number: 7782919
    Abstract: A buried semiconductor laser exhibiting a reduced dislocation of a contact layer is achieved. A buried semiconductor laser, comprising: an n-type indium phosphide (InP) substrate; an active layer disposed on the n-type InP substrate; block layers provided so as to bilaterally disposed on both sides of the active layer; a clad layer provided so as to cover the active layer and the block layers; and a p-type gallium indium arsenide (InGaAs) contact layer provided on the clad layer, wherein the p-type InGaAs contact layer has a compressive strain.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: August 24, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Satoshi Ae
  • Publication number: 20080137702
    Abstract: A buried semiconductor laser exhibiting a reduced dislocation of a contact layer is achieved. A buried semiconductor laser, comprising: an n-type indium phosphide (InP) substrate; an active layer disposed on the n-type InP substrate; block layers provided so as to bilaterally disposed on both sides of the active layer; a clad layer provided so as to cover the active layer and the block layers; and a p-type gallium indium arsenide (InGaAs) contact layer provided on the clad layer, wherein the p-type InGaAs contact layer has a compressive strain.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 12, 2008
    Applicant: NEC Electronics Corporation
    Inventor: Satoshi Ae
  • Patent number: 5790580
    Abstract: The invention provides a semiconductor optical integrated device which includes (a) a semiconductor layer, (b) a plurality of masks formed on the semiconductor layer, each of the masks having a shape varying in an axial direction of a light waveguide, and (c) quantum well structure selectively grown on the semiconductor layer by metal organic vapor phase epitaxy (MOVPE). The quantum well structure includes a well layer having a thickness and a bandgap wherein at least one of the thickness and bandgap in a region is different from those in another regions, a shape of said masks in the region being different from that in the another regions. The invention provides many advantages, one of which is that light waveguides having different bandgaps from one another can be formed on a common plane by single selective growth. This makes it possible to communicate regions to one another with high optical coupling ratio.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: August 4, 1998
    Assignee: NEC Corporation
    Inventors: Yasutaka Sakata, Takahiro Nakamura, Satoshi Ae
  • Patent number: 5785755
    Abstract: Disclosed are methods of preparing multilayer structures with InGaAsP layers of different compositions by metal organic vapor phase epitaxy, which result in formation of sharp heterointerfaces. After an InGaAsP well layer has been grown, the process is kept on standby with a flow of AsH.sub.3 and PH.sub.3, which are sources comprising elements of group V, at the well's composition ratios, and then with a flow of a source comprising an element of group V, including TBP (TBP/standby step), and an InGaAsP barrier layer is grown which has a smaller arsenic content than the well layer. TBP has a decomposition temperature approximately 100.degree. C. lower than PH.sub.3, and thus provides a phosphorus pressure which is five times or more as high as that of PH.sub.3 at identical growth temperatures and at identical V/III ratios.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: July 28, 1998
    Assignee: NEC Corporation
    Inventors: Takahiro Nakamura, Satoshi Ae