Patents by Inventor Satoshi Doi

Satoshi Doi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090014722
    Abstract: An active-matrix-drive LCD includes a TFT substrate, on which a TFT is formed. The TFT includes a gate electrode layer, a gate insulating film, a patterned semiconductor layer, and a source/drain electrode layer, which are consecutively formed on an insulating substrate of the TFT substrate. The gate electrode layer has a thickness smaller than a thickness of the gate insulating film.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 15, 2009
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventor: Satoshi Doi
  • Publication number: 20080026573
    Abstract: The invention provides a production method for an active matrix substrate in which a plurality of contact holes are formed by a one-mask process so as to reach metal films which are present at different depth positions in an insulating layer and are not evaporated by dry etching using a fluorine-containing gas. The method includes a step of performing dry etching using mixed gas of CHF3, CF4 and O2 to form the plurality of contact hole, a step of subjecting the plurality of contact holes to oxygen ashing, and a step of forming a transparent conductive film in the plurality of contact holes.
    Type: Application
    Filed: July 25, 2007
    Publication date: January 31, 2008
    Applicant: NEC LCD Technologies, Ltd.
    Inventors: Kiyoshi Yanase, Satoshi Doi
  • Publication number: 20070055013
    Abstract: A substrate for the immobilization of proteins is made by treating a carrier with an amino group-containing silicon compound represented by the following general formula: (RO)3Si—(CH2)k—(C6H4)1—(CH2)m—(NHCH2CH2)n—NH2 (wherein R is an alkyl group, and k is 1, 2, 3 . . . , l is 0, 1, 2, 3 . . . , m is 0, 1, 2, 3 . . . , and n is 1, 2, 3 . . . ).
    Type: Application
    Filed: February 21, 2006
    Publication date: March 8, 2007
    Inventors: Noriho Kamiya, Masahiro Goto, Satoshi Doi, Koichiro Nakamura, Noriyuki Kawata, Koji Fujita, Koki Tanamura
  • Publication number: 20060175286
    Abstract: A method for manufacturing a TFT panel of an LCD device includes the steps of wet etching a multilayer metallic structure including a high-melting-point metal film (HMPM) film, Al film and another HMPM film while using side etching technique by using a photoresist mask, hot-water washing the side walls of the Al film after the wet etching, and dry etching for configuring the channel region of a TFT in each pixel, and removing the photoresist mask. The presence of the photoresist mask and the protection film prevents corrosion of Al caused by plasma of the etching gas in the dry etching.
    Type: Application
    Filed: April 4, 2006
    Publication date: August 10, 2006
    Inventors: Hidekazu Matsushita, Tsuyoshi Katoh, Satoshi Doi, Akitoshi Maeda
  • Patent number: 7087624
    Abstract: Substituted pyrazole compounds represented by formula (I), or salts thereof are disclosed, wherein R1 is —CH(OH)—CH(R4)-(A)n-Y, —CH2—CH(R4)-(A)n-Y, —CO-B1-A-Y or the like (wherein A is a lower alkylene; Y is an aryl group which may be substituted, for example, by halogen, or the like; R4 is a hydrogen atom or a lower alkyl group; B1 is —CH(R4)— or —N(R4)—; and n is 0 or 1); R2 is a hydrogen atom, a lower alkyl group which may be substituted by hydroxyl or the like, or an aralkyl group; R3 is a phenyl group which may be substituted by halogen or the like, or a pyridyl group; and Q is a pyridyl or quinolyl group.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: August 8, 2006
    Assignee: Teikoju Hormone Mfg. Co., Ltd.
    Inventors: Nobuyoshi Minami, Michitaka Sato, Koichi Hasumi, Norio Yamamoto, Katsuyuki Keino, Teruaki Matsui, Arihiro Kanada, Shuji Ohta, Takahisa Saito, Shuichiro Sato, Akira Asagarasu, Satoshi Doi, Motohiro Kobayashi, Jun Sato, Hajime Asano
  • Publication number: 20060146220
    Abstract: A liquid crystal display is fabricated which has bus wires disposed in a grid shape, switching elements coupled to the bus wires, and pixel electrodes which are disposed on an interlayer insulating film formed by coating and which are coupled with the switching elements. In fabricating the liquid crystal display, when a transparent conductive film is formed on the interlayer insulating film which is formed by coating, the temperature of the substrate is controlled to become 100° C.-170° C. In another embodiment, when the transparent conductive film is formed on the interlayer insulating film in a non-heated condition, an oxygen flow rate ratio is set to 1% or lower, and annealing is performed after forming the film. Thereby, when etching the ITO film on the interlayer insulating film, etching residue is not produced. Further, contact resistance between the ITO film and the lower layer metal can be uniformly decreased, and display defects can be obviated.
    Type: Application
    Filed: February 27, 2006
    Publication date: July 6, 2006
    Inventors: Shigeru Kimura, Akitoshi Maeda, Satoshi Doi, Takayuki Ishino
  • Patent number: 6890783
    Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: May 10, 2005
    Assignee: NEC LCD Technologies, LTD.
    Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
  • Patent number: 6872603
    Abstract: A method of fabricating a semiconductor device including an interconnection is provided. The method is composed of covering a substrate with a metal film stack including a lower refractory metal film over the substrate, a lower protective layer of a first compound including metal disposed on an upper surface of the lower refractory metal film, a core metal film of the metal on an upper surface of the lower protective layer, an upper protective layer of a second compound including the metal disposed on an upper surface of the core metal film, and an upper refractory metal film disposed on an upper surface of the upper protective layer, patterning the metal film stack; and forming a side protective layer of a third compound including the metal on a side of the patterned core metal film.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: March 29, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Satoshi Doi
  • Publication number: 20040134878
    Abstract: A method for manufacturing a TFT panel of an LCD device includes the steps of wet etching a multilayer metallic structure including a high-melting-point metal film (HMPM) film, Al film and another HMPM film while using side etching technique by using a photoresist mask, hot-water washing the side walls of the Al film after the wet etching, and dry etching for configuring the channel region of a TFT in each pixel, and removing the photoresist mask. The presence of the photoresist mask and the protection film prevents corrosion of Al caused by plasma of the etching gas in the dry etching.
    Type: Application
    Filed: November 12, 2003
    Publication date: July 15, 2004
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventors: Hidekazu Matsushita, Tsuyoshi Katoh, Satoshi Doi, Akitoshi Maeda
  • Publication number: 20040097024
    Abstract: A method of fabricating a semiconductor device including an interconnection is provided. The method is composed of covering a substrate with a metal film stack including a lower refractory metal film over the substrate, a lower protective layer of a first compound including metal disposed on an upper surface of the lower refractory metal film, a core metal film of the metal on an upper surface of the lower protective layer, an upper protective layer of a second compound including the metal disposed on an upper surface of the core metal film, and an upper refractory metal film disposed on an upper surface of the upper protective layer, patterning the metal film stack; and forming a side protective layer of a third compound including the metal on a side of the patterned core metal film.
    Type: Application
    Filed: November 13, 2003
    Publication date: May 20, 2004
    Applicant: NEC LCD Technolongies, Ltd.
    Inventor: Satoshi Doi
  • Publication number: 20040087628
    Abstract: Substituted pyrazole compounds represented by formula (I), or salts thereof are disclosed, wherein R1 is —CH(OH)—CH(R4)-(A)n —Y, —CH2 —CH(R4)-(A)n—Y, —CO—B1-A-Y or the like (wherein A is a lower alkylene; Y is an aryl group which may be substituted, for example, by halogen, or the like; R4 is a hydrogen atom or a lower alkyl group; B1 is —CH(R4)— or —N(R4)—; and n is 0 or 1); R2 is a hydrogen atom, a lower alkyl group which may be substituted by hydroxyl or the like, or an aralkyl group; R3 is a phenyl group which may be substituted by halogen or the like, or a pyridyl group; and Q is a pyridyl or quinolyl group. These substituted pyrazole compounds or their salts have an excellent p38MAP kinase inhibiting effect and are hence useful in the prevention or treatment of tumor necrosis factor &agr;-related diseases, interleukin 1-related diseases, interleukin 6-related diseases or cyclooxygenase II-related diseases.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 6, 2004
    Inventors: Nobuyoshi Minami, Michitaka Sato, Koichi Hasumi, Norio Yamamoto, Katsuyuki Keino, Teruaki Matsui, Arihiro Kanada, Shuji Ohta, Takahisa Saito, Shuichiro Sato, Akira Asagarasu, Satoshi Doi, Motohiro Kobayashi, Jun Sato, Hajime Asano
  • Patent number: 6667325
    Abstract: Substituted pyrazole compounds represented by formula (I), or salts thereof are disclosed, wherein R1 is —CH(OH)—CH(R4)—(A)n—Y, —CH2—CH(R4)—(A)n—Y, —CO—B1—A—Y or the like (wherein A is a lower alkylene; Y is an aryl group which may be substituted, for example, by halogen, or the like; R4 is a hydrogen atom or a lower alkyl group; B1 is —CH(R4)— or —N(R4)—; and n is 0 or 1); R2 is a hydrogen atom, a lower alkyl group which may be substituted by hydroxyl or the like, or an aralkyl group; R3 is a phenyl group which may be substituted by halogen or the like, or a pyridyl group; and Q is a pyridyl or quinolyl group. These substituted pyrazole compounds or their salts have an excellent p38MAP kinase inhibiting effect and are hence useful in the prevention or treatment of tumor necrosis factor &agr;-related diseases, interleukin 1-related diseases, interleukin 6-related diseases or cyclooxygenase II-related diseases.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: December 23, 2003
    Assignee: Teikoku Hormone Mfg. Co., Ltd.
    Inventors: Nobuyoshi Minami, Michitaka Sato, Koichi Hasumi, Norio Yamamoto, Katsuyuki Keino, Teruaki Matsui, Arihiro Kanada, Shuji Ohta, Takahisa Saito, Shuichiro Sato, Akira Asagarasu, Satoshi Doi, Motohiro Kobayashi, Jun Sato, Hajime Asano
  • Patent number: 6632696
    Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: October 14, 2003
    Assignee: NEC Corporation
    Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
  • Patent number: 6511997
    Abstract: Aminopyrazole derivatives represented by formula (I), or salts thereof, wherein X1 and X2 are each a hydrogen atom or a halogen atom, or X1 and X2 may be united together to form a lower alkylenedioxy group, Q is a pyridyl group or a quinolyl group, R1 is a hydrogen atom, a substituted or unsubstituted lower alkyl or aryl group, R2 is a hydrogen atom, a lower alkyl group, or an aralkyl group, and R3 represents a hydrogen atom, an organic sulfonyl group, or —C(═Y)—R4 in which R4 is a hydrogen atom or an organic residue and Y is an oxygen or sulfur atom, provided that, when R3 is a hydrogen atom, R1 is a group other than a hydrogen atom and R2 is a hydrogen atom. These amimopyrazole derivatives or their salts have excellent p38MAP kinase inhibiting activities and are hence useful in the prevention or treatment of diseases associated with tumor necrosis sis factor &agr;, interleukin 1, interleukin 6 or cyclooxygenase II.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: January 28, 2003
    Assignee: Teikoku Hormone Mfg. Co., Ltd.
    Inventors: Nobuyoshi Minami, Michitaka Sato, Koichi Hasumi, Norio Yamamoto, Katsuyuki Keino, Teruaki Matsui, Arihiro Kanada, Shuji Ohta, Takahisa Saito, Shuichiro Sato, Akira Asagarasu, Satoshi Doi, Motohiro Kobayashi, Jun Sato, Hajime Asano
  • Publication number: 20030013221
    Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.
    Type: Application
    Filed: September 12, 2002
    Publication date: January 16, 2003
    Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
  • Publication number: 20020140895
    Abstract: A liquid crystal display is fabricated which has bus wires disposed in a grid shape, switching elements coupled to the bus wires, and pixel electrodes which are disposed on an interlayer insulating film formed by coating and which are coupled with the switching elements. In fabricating the liquid crystal display, when a transparent conductive film is formed on the interlayer insulating film which is formed by coating, the temperature of the substrate is controlled to become 100° C.-170° C. In other way, when the transparent conductive film is formed on the interlayer insulating film in a non-heated condition, an oxygen flow rate ratio is set to 1% or lower, and annealing is performed after forming the film. Thereby, when etching the ITO film on the interlayer insulating film, etching residue is not produced. Further, contact resistance between the ITO film and the lower layer metal can be uniformly decreased, and display defects can be obviated.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 3, 2002
    Applicant: NEC CORPORATION
    Inventors: Shigeru Kimura, Akitoshi Maeda, Satoshi Doi, Takayuki Ishino
  • Publication number: 20010010370
    Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.
    Type: Application
    Filed: December 20, 2000
    Publication date: August 2, 2001
    Applicant: NEC Corporation
    Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
  • Patent number: 5900161
    Abstract: For use with CVD apparatus, an apparatus and method for detecting the end point of a post treatment after an in-situ cleaning operation is provided such that reactive chemical species which remain after an in-situ cleaning operation can be accurately removed so that they do not cause harm to a film formed after the cleaning operation. The end point detection apparatus includes a reactor, an RF electrode, an RF power supply, a gas supply pipe for forming a thin film, a gas supply pipe for in-situ cleaning, a detector for detecting discharge characteristic values (i.e. the self-bias voltage, the electrode voltage, and the discharge impedance) during the post treatment performed after the in-situ cleaning, and a monitor/determining circuit for monitoring an output from the detector.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: May 4, 1999
    Assignee: Anelva Corporation
    Inventor: Satoshi Doi
  • Patent number: 5830310
    Abstract: For use with CVD apparatus, an apparatus and method for detecting the end point of a post treatment after an in-situ cleaning operation is provided such that reactive chemical species which remain after an in-situ cleaning operation can be accurately removed so that they do not cause harm to a film formed after the cleaning operation. The end point detection apparatus includes a reactor, an RF electrode, an RF power supply, a gas supply pipe for forming a thin film, a gas supply pipe for in-situ cleaning, a detector for detecting discharge characteristic values (i.e. the self-bias voltage, the electrode voltage, and the discharge impedance) during the post treatment performed after the in-situ cleaning, and a monitor/determining circuit for monitoring an output from the detector.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: November 3, 1998
    Assignee: Anelva Corporation
    Inventor: Satoshi Doi
  • Patent number: D500098
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: December 21, 2004
    Assignee: Sega Corporation
    Inventor: Satoshi Doi