Abstract: An information processing device includes an associator, an extractor, and an outputter. The associator is configured to associate each of a series of pieces of history data related to at least any of deposits and withdrawals of a user with any of a plurality of behaviors related to an economic activity of the user. The extractor is configured to extract an inducement destination candidate according to behavioral characteristics of the user based on changes along a time series of each of the plurality of behaviors. The outputter is configured to output information indicating the extracted inducement destination candidate to a predetermined output destination.

Abstract: A digital phase-locked loop circuit includes: a first counter which counts a first clock; a second counter which counts third clocks into which a second clock is divided; a first phase detector which detects a relative phase difference between the first and the third clocks according to a first comparison result that clocks in which the third clock is delayed are compared with the first clock and a second comparison result that clocks in which the first clock is delayed are compared with the third clock; a second phase detector which measures the period of the second clock; a phase error calculating unit which calculates a phase difference between the first and the third clocks according to the value that the result detected by the first phase detector is normalized by the result detected by the second phase detector and the count values of the first and the second counters; and a DCO which outputs the second clock according to the result calculated by the phase error calculating unit.

Abstract: A voltage-controlled oscillator includes a delay circuit. The delay circuit includes a first buffer inverter which receives one of the differential input signal and outputs an other of the differential output signal, a second buffer inverter which receives the other of the differential input signal and outputs the one of the differential output signal, a first latch inverter which receives the one of the differential output signal, and includes an output connected to an output of the first buffer inverter, and a second latch inverter which receives the other of the differential output signal, and includes an output connected to an output of the second buffer inverter. The first latch inverter and the first buffer inverter receive a current produced from different voltage-current conversion circuits.

Abstract: A multi-phase clock generation circuit including a phase interpolation circuit that generates and outputs an interpolation signal based on first and second clock signals, the interpolation signal interpolating a phase between output clock signals corresponding to the first and the second clock signals, and a control circuit that generates a first control signal to adjust a phase of the interpolation signal and outputs the first control signal to the phase interpolation circuit, in which the control circuit includes a timing detection circuit that detects a timing of a change in a logic value of the interpolation signal, and a control signal generation circuit that generates the first control signal according to a detection result in the timing detection circuit.

Abstract: A digital phase-locked loop circuit includes: a first counter which counts a first clock; a second counter which counts third clocks into which a second clock is divided; a first phase detector which detects a relative phase difference between the first and the third clocks according to a first comparison result that clocks in which the third clock is delayed are compared with the first clock and a second comparison result that clocks in which the first clock is delayed are compared with the third clock; a second phase detector which measures the period of the second clock; a phase error calculating unit which calculates a phase difference between the first and the third clocks according to the value that the result detected by the first phase detector is normalized by the result detected by the second phase detector and the count values of the first and the second counters; and a DCO which outputs the second clock according to the result calculated by the phase error calculating unit.

Abstract: A voltage-controlled oscillator includes a delay circuit. The delay circuit includes a first buffer inverter which receives one of the differential input signal and outputs an other of the differential output signal, a second buffer inverter which receives the other of the differential input signal and outputs the one of the differential output signal, a first latch inverter which receives the one of the differential output signal, and includes an output connected to an output of the first buffer inverter, and a second latch inverter which receives the other of the differential output signal, and includes an output connected to an output of the second buffer inverter. The first latch inverter and the first buffer inverter receive a current produced from different voltage-current conversion circuits.

Abstract: A Phase-Locked Loop (PLL) circuit includes a voltage-controlled oscillator. The voltage-controlled oscillator includes a voltage-current conversion circuit and a current-controlled oscillation circuit. The voltage-current conversion circuit includes an input transistor having a gate terminal connecting a control voltage, a first transistor connected in series to the input transistor, a second transistor connected as a current-mirror to the first transistor, to generate a control current, and a current source connected in parallel to the first transistor. The current-controlled oscillation circuit oscillates at a frequency according to the control current.

Abstract: In a pulse width modulation circuit, a multiphase clock generation section generates a multiphase clock signal according to a reference clock. Then, a pulse width modulation signal is generated according to input data and the multiphase clock signal generated by the multiphase clock generation section. The multiphase clock generation section has a phase lock loop circuit and generates the multiphase clock signal by phase-interpolating an intermediate clock signal generated by the phase lock loop circuit.

Abstract: In a pulse width modulation circuit, a multiphase clock generation section generates a multiphase clock signal according to a reference clock. Then, a pulse width modulation signal is generated according to input data and the multiphase clock signal generated by the multiphase clock generation section. The multiphase clock generation section has a phase lock loop circuit and generates the multiphase clock signal by phase-interpolating an intermediate clock signal generated by the phase lock loop circuit.

Abstract: A tape run control unit in the magnetic recording/reproducing apparatus is provided with a discrimination element and a control element. The discrimination element detects a stand-by time until a signal to be recorded is received in repositioning of the tape and generates a discrimination signal for discriminating the length of the stand-by time. The control element controls tape run driving unit such as a capstan motor during the reposition and controls the stop position of the tape such that a magnetic head scans the portion of the tape where no data is recorded. After completion of repositioning, furthermore, the control element works according to a discrimination signal so as to select the stop mode which involves the release of pinch roller when the stand-by time is long and to select the mode for simply stopping only the capstan when the stand-by time is short.

Abstract: A tape run control unit in a magnetic recording and reproducing apparatus is provided with a discriminator and on a controller. The discriminator detects a stand-by time until a signal to be recorded is received in repositioning of the tape and generates a discrimination signal for discriminating the length of the stand-by time. The controller controls tape driving unit such as a capstan motor during the reposition and controls the stop position of the tape such that a magnetic head scans the portion of the tape where no data is recorded. After completion of repositioning, furthermore, the controller is responsive to a discrimination signal so as to select the stop mode which involves the release of pinch roller when the stand-by time is long and to select the mode for simply stopping only the capstan when the stand-by time is short.