Patents by Inventor Satoshi Hiramoto

Satoshi Hiramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Simulation method and simulation apparatus
    Patent number: 8428927
    Abstract: A simulation method includes obtaining an execution log generated while a predetermined processing is executed by simulating a series of operations in a test model that is a modeled version of a test target device by causing a predetermined processing to be executed in the test model, extracting a processing unit log constituted by a predetermined processing unit from the execution log obtained in the obtaining, and simulating an operation in which processing corresponding to the processing unit log extracted in the extracting is executed in a test model in which a part of function of the test target device is modified, the operation being simulated on the basis of a setting condition set by a user.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: April 23, 2013
    Assignee: Fujitsu Limited
    Inventors: Noriyasu Nakayama, Nobukazu Koizumi, Tomoki Kato, Naoki Yuzawa, Hiroyuki Hieda, Satoshi Hiramoto
  • Performance evaluation simulation
    Patent number: 8214189
    Abstract: A performance evaluation simulation apparatus divides a process into basic process units based on an execution log, calculates a throughput of each basic process unit from information held in the execution log, changes an arrangement structure so that a basic process unit with the calculated throughput exceeding a predetermined threshold is disposed in a hardware model, and performs a performance evaluation simulation on the hardware model and a software model to generate statistical information on which performance evaluation is based.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: July 3, 2012
    Assignee: Fujitsu Limited
    Inventors: Tomoki Kato, Nobukazu Koizumi, Noriyasu Nakayama, Naoki Yuzawa, Hiroyuki Hieda, Satoshi Hiramoto
  • Simulation method, electronic apparatus design method, and simulation apparatus
    Publication number: 20100204975
    Abstract: A simulation method includes obtaining an execution log generated while a predetermined processing is executed by simulating a series of operations in a test model that is a modeled version of a test target device by causing a predetermined processing to be executed in the test model, extracting a processing unit log constituted by a predetermined processing unit from the execution log obtained in the obtaining, and simulating an operation in which processing corresponding to the processing unit log extracted in the extracting is executed in a test model in which a part of function of the test target device is modified, the operation being simulated on the basis of a setting condition set by a user.
    Type: Application
    Filed: April 13, 2010
    Publication date: August 12, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Noriyasu Nakayama, Nobukazu Koizumi, Tomoki Kato, Naoki Yuzawa, Hiroyuki Hieda, Satoshi Hiramoto
  • Performance evaluation simulation
    Publication number: 20090204380
    Abstract: A performance evaluation simulation apparatus divides a process into basic process units based on an execution log, calculates a throughput of each basic process unit from information held in the execution log, changes an arrangement structure so that a basic process unit with the calculated throughput exceeding a predetermined threshold is disposed in a hardware model, and performs a performance evaluation simulation on the hardware model and a software model to generate statistical information on which performance evaluation is based.
    Type: Application
    Filed: December 8, 2008
    Publication date: August 13, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Tomoki Kato, Nobukazu Koizumi, Noriyasu Nakayama, Naoki Yuzawa, Hiroyuki Hieda, Satoshi Hiramoto