Patents by Inventor Satoshi Hiyamizu

Satoshi Hiyamizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5951756
    Abstract: A method of forming GaAs/AlGaAs hetero-structure. The method includes the steps of preparing a GaAs substrate having a (411)A-oriented surface and setting the GaAs substrate inside a growth container with the (411)A surface being disposed as a surface to be deposited. The pressure inside the growth chamber is reduced and the GaAs substrate is heated up to a predetermined temperature to cause epitaxial growth of Ga, Al, As on the (411)A substrate and forming a GaAs/AlGaAs hetero-structure on the (411)A-oriented GaAs substrate.
    Type: Grant
    Filed: February 13, 1996
    Date of Patent: September 14, 1999
    Assignee: Kubota Corporation
    Inventors: Satoshi Hiyamizu, Satoshi Shimomura, Yasunori Okamoto
  • Patent number: 5679179
    Abstract: A method of forming GaAs/AlGaAs hetero-structure. The method includes the steps of preparing a GaAs substrate having a (411)A-oriented surface and setting the GaAs substrate inside a growth container with the (411)A surface being disposed as a surface to be deposited. The pressure inside the growth chamber is reduced and the GaAs substrate is heated up to a predetermined temperature to cause epitaxial growth of Ga, Al, As on the (411)A substrate and forming a GaAs/AlGaAs hetero-structure on the (411)A-oriented GaAs substrate.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: October 21, 1997
    Assignee: Kubota Corporation
    Inventors: Satoshi Hiyamizu, Satoshi Shimomura, Yasunori Okamoto
  • Patent number: 4833508
    Abstract: A field effect semiconductor device which utilizes a 2DEG and is composed of a semi-insulating GaAs substrate; an i-type GaAs active layer; a superlattice structure layer which comprises a first i-type AlAs thin layer, a GaAs thin layer doped with an Si atomic plane, and a second i-type AlAs thin layer, these thin layers forming a GaAs quantum well; and n-type AlGaAs layer; and electrodes for source, drain, and gate.
    Type: Grant
    Filed: December 7, 1987
    Date of Patent: May 23, 1989
    Assignee: Fujitsu Limited
    Inventors: Tomonori Ishikawa, Shigehiko Sasa, Satoshi Hiyamizu
  • Patent number: 4799088
    Abstract: A high electron mobility single heterojunction semiconductor devices having a layer configuration comprising a N-type AlGaAs layer grown on an undoped GaAs layer grown on an undoped AlGaAs layer grown on a semiconductor substrate containing an impurity producing a deep level. The undoped AlGaAs layer has at least three functions including (a) a getter for the deep level impurity which may be diffused from the substrate during an annealing process, (b) a buffer improving the crystal condition of the undoped GaAs layer, and (c) a test layer grown for the purpose of predetermining the intensity of molecular or ion beams for each of Al, Ga, As and dopants e.g. Si. This allows annealing processes and ion implantation processes to be introduced to the method for production of this type of semiconductor devices without reducing the electron mobility thereof.
    Type: Grant
    Filed: July 27, 1981
    Date of Patent: January 17, 1989
    Assignee: Fujitsu Limited
    Inventors: Satoshi Hiyamizu, Toshio Fujii
  • Patent number: 4714948
    Abstract: The present invention is related to an improvement of a high-electron mobility transistor (HEMT) which has an undoped GaAs layer and an N-doped AlGaAs layer a heterojunction formed between the undoped GaAs layer and the N-doped AlGaAs layer, respectively a gate electrode on the N-doped AlGaAs layer, and an electron-storing layer formed in proximity to the heterojunction due to the difference in electron affinity between the undoped GaAs layer and the N-doped AlGaAs layer. The known HEMT has a disadvantage in that during the formation of the source and drain regions by means of, for example, thermal diffusion, the impurities of the N-doped AlGaAs layer may diffuse into the undoped GaAs layer through the heterojunction so that the mobility of the electrons in the electron-storing layer is lessened. This disadvantage is removed in the present invention by the provision of a conduction layer formed by the epitaxial growth of highly-doped GaAs.
    Type: Grant
    Filed: March 13, 1986
    Date of Patent: December 22, 1987
    Assignee: Fujitsu Limited
    Inventors: Takashi Mimura, Satoshi Hiyamizu