Patents by Inventor Satoshi Hoshina
Satoshi Hoshina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8130832Abstract: A video decoding device includes: a decoder that decodes an encoded video bit stream to generate a prediction error signal; a motion compensator that performs a motion compensation prediction using a motion vector that refers at least one picture to generate a motion compensation prediction signal; a weighted predictor that generates a weighted prediction signal from a linear sum of (1) a product of the motion compensation prediction signal and a first weighting coefficient and (2) a second weighting coefficient; a selector that selects one of the motion compensation prediction signal and the weighted prediction signal; and an adder that adds (1) selected one of the weighted prediction signal and the motion compensation prediction signal and (2) the prediction error signal.Type: GrantFiled: September 18, 2007Date of Patent: March 6, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Noriaki Kitada, Katsuhisa Yano, Kosuke Uchida, Satoshi Hoshina
-
Patent number: 8040951Abstract: An information processing apparatus includes a unit that executes a de-blocking filter process for each of decoded pictures, a unit that executes a motion compensation prediction process that generates an inter-frame prediction signal, from one or more pictures that are subjected to the de-blocking filter process, a unit that executes an intra-frame prediction process that generates an intra-frame prediction signal, a unit that adds one of the inter-frame prediction signal and the intra-frame prediction signal to a prediction error signal corresponding to the to-be-decoded picture to decode the to-be-decoded picture, and a unit that executes, when a load on the information processing apparatus is greater than a predetermined reference value, a process that skips execution of the de-blocking filter process and generates the inter-frame prediction signal, which corresponds to the to-be-decoded picture, from the one or more decoded pictures that are not subjected to the de-blocking filter process.Type: GrantFiled: August 24, 2005Date of Patent: October 18, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Noriaki Kitada, Kosuke Uchida, Satoshi Hoshina, Yoshihiro Kikuchi, Yuji Kawashima
-
Patent number: 7961791Abstract: A decoding apparatus includes a decoder configured to receive a series of encoded pictures and to decode each of the encoded pictures to produce a series of decoded pictures, each of the encoded pictures being either intra-encoded or inter-encoded, and each of the decoded pictures being either referred or, non-referred, a blocking noise suppressor configured to suppress blocking noise of each of the decoded pictures, and a controller configured to detect an amount of a load, to run each of the referred decoded pictures through the blocking noise suppressor if the detected amount of the load is no lower than a given threshold, and to have each of the non-referred decoded pictures bypass the blocking noise suppressor if the detected amount of the load is no lower than the threshold.Type: GrantFiled: March 21, 2006Date of Patent: June 14, 2011Assignee: Kabushiki Kaisha TOSHIBAInventors: Yuji Kawashima, Yoshihiro Kikuchi, Tatsuro Fujisawa, Noriaki Kitada, Kosuke Uchida, Satoshi Hoshina
-
Patent number: 7653253Abstract: When a quantized DCT coefficient and a quantization parameter are input from an entropy decoder, a controller outputs them to a switch and gives a load detector an instruction to detect system load. The load detector requests system load information from OS. If the system load is light, the load detector controls the switch to execute first inverse quantization of general load by a general processor and obtain a DCT coefficient. If the system load is heavy, the load detector controls the switch to execute second inverse quantization whose processing load is lighter than the first inverse quantization by a specific processor and obtain a DCT coefficient.Type: GrantFiled: March 20, 2006Date of Patent: January 26, 2010Assignee: Kabushiki Kaisha TOSHIBAInventors: Tatsuro Fujisawa, Yoshihiro Kikuchi, Yuji Kawashima, Noriaki Kitada, Kosuke Uchida, Satoshi Hoshina
-
Publication number: 20080240244Abstract: A video decoding device includes: a decoder that decodes an encoded video bit stream to generate a prediction error signal; a motion compensator that performs a motion compensation prediction using a motion vector that refers at least one picture to generate a motion compensation prediction signal; a weighted predictor that generates a weighted prediction signal from a linear sum of (1) a product of the motion compensation prediction signal and a first weighting coefficient and (2) a second weighting coefficient; a selector that selects one of the motion compensation prediction signal and the weighted prediction signal; and an adder that adds (1) selected one of the weighted prediction signal and the motion compensation prediction signal and (2) the prediction error signal.Type: ApplicationFiled: September 18, 2007Publication date: October 2, 2008Inventors: Noriaki Kitada, Katsuhisa Yano, Kosuke Uchida, Satoshi Hoshina
-
Publication number: 20080240236Abstract: An information processing apparatus is for decoding a video encoded sequence and includes: a CPU that decodes the video encoded sequence by executing software; a GPU that decodes the video encoded sequence; a main memory that temporarily stores data for the decoding process performed by the CPU; and a VRAM that temporarily stores data for the decoding process performed by the GPU, wherein the GPU continues the decoding process of subsequent pictures of at least the second and third pictures after the GPU decoded the referenced third picture, until the refresh first picture is subjected to the decoding process.Type: ApplicationFiled: September 6, 2007Publication date: October 2, 2008Inventors: Kosuke Uchida, Katsuhisa Yano, Noriaki Kitada, Satoshi Hoshina
-
Publication number: 20080031356Abstract: According to one embodiment, an information processing apparatus includes a determination unit configured to determine an encoded status of an encoded moving image data, an estimation unit configured to estimate a decoding load of the moving image data based on the encoded status of the moving image data determined by the determination unit, and a control unit configured to omit a part of a decoding process for decoding the moving image data based on the decoding load of the moving image data estimated by the estimation unit.Type: ApplicationFiled: July 12, 2007Publication date: February 7, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kosuke Uchida, Noriaki Kitada, Satoshi Hoshina
-
Publication number: 20070274688Abstract: According to one embodiment, a moving image playback apparatus has a structure wherein a decoder is initialized when a CPU first detects an SPS-equipped I-picture in playback of a video stream of an HD DVD, and the decoder decodes the video stream.Type: ApplicationFiled: November 17, 2006Publication date: November 29, 2007Inventors: Noriaki Kitada, Kosuke Uchida, Satoshi Hoshina
-
Publication number: 20070177669Abstract: Provided is a decoding apparatus comprising a decoder configured to receive a series of encoded pictures and to decode each of the encoded pictures to produce a series of decoded pictures, each of the encoded pictures being either intra-encoded or inter-encoded, and each of the decoded pictures being either referred or nonreferred, a blocking noise suppressor configured to suppress blocking noise of each of the decoded pictures, and a controller configured to detect an amount of a load, to run each of the decoded pictures through the blocking noise suppressor if the detected amount of the load is lower than a given threshold, to have each of the decoded pictures being non-referred bypass the blocking noise suppressor if the detected amount of the load is no lower than the threshold, and to transmit each of the decoded pictures either having been run through or having bypassed the blocking noise suppressor.Type: ApplicationFiled: March 21, 2006Publication date: August 2, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuji Kawashima, Yoshihiro Kikuchi, Tatsuro Fujisawa, Noriaki Kitada, Kosuke Uchida, Satoshi Hoshina
-
Publication number: 20070172136Abstract: When a quantized DCT coefficient and a quantization parameter are input from an entropy decoder, a controller outputs them to a switch and gives a load detector an instruction to detect system load. The load detector requests system load information from OS. If the system load is light, the load detector controls the switch to execute first inverse quantization of general load by a general processor and obtain a DCT coefficient. If the system load is heavy, the load detector controls the switch to execute second inverse quantization whose processing load is lighter than the first inverse quantization by a specific processor and obtain a DCT coefficient.Type: ApplicationFiled: March 20, 2006Publication date: July 26, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuro Fujisawa, Yoshihiro Kikuchi, Yuji Kawashima, Noriaki Kitada, Kosuke Uchida, Satoshi Hoshina
-
Publication number: 20070140355Abstract: According to one embodiment, an information processing apparatus which decodes a compression encoded moving image stream, includes a filter processing unit which executes a deblocking filter process in order to reduce block distortion for each decoded picture, a detection unit which detects a load state of the information processing apparatus, and a control unit which causes the filter processing unit to execute the deblocking filter process without a process for a color difference signal in accordance with the load state detected by the detection unit.Type: ApplicationFiled: December 7, 2006Publication date: June 21, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kosuke Uchida, Noriaki Kitada, Satoshi Hoshina
-
Publication number: 20060204221Abstract: A video reproduction application program monitors whether or not blend processing for superimposing one of two images on the other is executed, and executes all decode processings (normal decode processings), when the blend processing is not executed. On the other hand, when the blend processing is executed, a specific processing is executed in which decoding of a color component is omitted from decode processing for decoding the images to be subjected to the blend processing. As a result, the load on the system is reduced.Type: ApplicationFiled: February 13, 2006Publication date: September 14, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kosuke Uchida, Noriaki Kitada, Satoshi Hoshina
-
Publication number: 20060203910Abstract: According to one embodiment, there is provided an information processing apparatus, including a decoding unit which decodes a moving image stream that is compressed and coded, a deblocking filtering unit which performs a deblocking filtering process for a picture included in the moving image stream to reduce a block distortion, a blending unit which performs a blending process of superimposing a second picture on a first picture with designated transparency, and a control unit which determines whether the blending process is performed for the picture included in the moving image stream and, when the blending process is performed, varies an amount of processing of the deblocking filtering process for at least one of the first and second pictures in accordance with the transparency.Type: ApplicationFiled: March 14, 2006Publication date: September 14, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Noriaki Kitada, Kosuke Uchida, Satoshi Hoshina, Yoshihiro Kikuchi, Yuji Kawashima
-
Publication number: 20060203917Abstract: According to one embodiment, an information processing apparatus having a decoder to decode encoded streaming data to be displayed to form a picture including a plurality of blocks comprises a filtering unit for filtering the decoded streaming data to reduce distortion of the block with respect to each picture, a detecting unit for detecting a size of the picture to be displayed, and a simplifying unit for simplifying the filtering by the filtering unit in response to the size of the picture detected by the detecting unit.Type: ApplicationFiled: September 8, 2005Publication date: September 14, 2006Inventors: Kosuke Uchida, Noriaki Kitada, Satoshi Hoshina, Yoshihiro Kikuchi, Yuji Kawashima
-
Publication number: 20060203909Abstract: According to one embodiment, there is provided an information processing apparatus including a decoding unit which decodes a moving image stream that is compressed and coded, a processing unit which performs a deblocking filtering process for a picture included in the moving image stream to reduce a block distortion, and a control unit which varies an amount of processing of the deblocking filtering process in accordance with a given condition.Type: ApplicationFiled: March 10, 2006Publication date: September 14, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Noriaki Kitada, Kosuke Uchida, Satoshi Hoshina, Yoshihiro Kikuchi, Yuji Kawashima
-
Publication number: 20060067406Abstract: An information processing apparatus includes a unit that executes a de-blocking filter process for each of decoded pictures, a unit that executes a motion compensation prediction process that generates an inter-frame prediction signal, from one or more pictures that are subjected to the de-blocking filter process, a unit that executes an intra-frame prediction process that generates an intra-frame prediction signal, a unit that adds one of the inter-frame prediction signal and the intra-frame prediction signal to a prediction error signal corresponding to the to-be-decoded picture to decode the to-be-decoded picture, and a unit that executes, when a load on the information processing apparatus is greater than a predetermined reference value, a process that skips execution of the de-blocking filter process and generates the inter-frame prediction signal, which corresponds to the to-be-decoded picture, from the one or more decoded pictures that are not subjected to the de-blocking filter process.Type: ApplicationFiled: August 24, 2005Publication date: March 30, 2006Inventors: Noriaki Kitada, Kosuke Uchida, Satoshi Hoshina, Yoshihiro Kikuchi, Yuji Kawashima
-
Publication number: 20030084243Abstract: There is disclosed a network controller which is disposed in a disk controller and which transmits read fractionated data to a host computer as a requester every read end of each of disk apparatuses having ended the reading without waiting for the read end of the disk apparatuses constituting the disk array.Type: ApplicationFiled: October 24, 2002Publication date: May 1, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Hoshina, Toshimitsu Noguchi
-
Patent number: 5931954Abstract: In a computer system, when a CPU performs a state setting operation, such as setting an appropriate operation mode for I/O devices, the log data of the state setting operation is stored in a log storage area. Upon occurrence of a fault in the computer system, the I/O devices are cleared, and the state setting operation of the I/O devices is performed on the basis of the log data of the prior state setting operation stored in the log storage area. Therefore, the states of the I/O devices can be recovered to a state at a checkpoint when the process is restarted.Type: GrantFiled: January 13, 1997Date of Patent: August 3, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Hoshina, Takeshi Sakuma, Hiroshi Sakai
-
Patent number: 5828821Abstract: Log memories for recording updated history of a main memory are provided. CPUs record the updated history of the main memory to either of the log memories and writes context thereof and content of a cache memory to the main memory at a checkpoint acquisition. The updated history of the main memory is switched from one of CPUs that has finished a checkpoint processing to other one of the log memories in which the CPUs do not use to record the updated history of the main memory. Normal processing is restarted without waiting for finishing the checkpoint acquisition of the other ones of CPUs.Type: GrantFiled: June 18, 1996Date of Patent: October 27, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Hoshina, Hiroshi Sakai, Hideaki Hirayama, Shigefumi Ohmori, Takahiro Fujii, Yoshio Masubuchi