Abstract: One paired wiring traveling in parallel to a transmission path of a signal and a transmission path of reference voltage is used, and a terminal end resistor matched with the characteristic impedance is installed, and in a receiving circuit connected thereto, a differential input circuit with offset set to about 1/2 of the terminal end voltage is used, and an output circuit of open drain is used in a transmitting circuit. A high-speed information processing section using such a bus circuit and a low-speed information processing section using a conventional low-speed bus are mutually connected through an interface circuit to construct the system hierarchically.

Abstract: A large scale integrated circuit including therein a logical gate circuit and a memory circuit is disclosed in which a large number of circuit blocks each having the same structure and including at least eight transistors and at least five resistors are arranged on a chip, and the logical gate circuit or memory circuit has a selected wiring pattern of the transistors and resistors included in the circuit block.