Patents by Inventor Satoshi Iida
Satoshi Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11964507Abstract: A method for producing a printed material includes forming a color image having an image area ratio of 20% or less on a peripheral edge portion of a recording medium by using a coloring material; providing pressure-induced phase transition particles to a region of the recording medium, the region including the peripheral edge portion; bonding the color image and the pressure-induced phase transition particles onto the recording medium; and folding the recording medium having the color image and the pressure-induced phase transition particles bonded thereon and pressure-bonding the folded recording medium, or pressure-bonding the recording medium having the color image and the pressure-induced phase transition particles bonded thereon and another recording medium placed on top of each other.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Sumiaki Yamasaki, Sakae Takeuchi, Hiroshi Saegusa, Yoichiro Emura, Yoshifumi Iida, Satoshi Kamiwaki, Susumu Yoshino
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Patent number: 11965044Abstract: Pressure-responsive particles include pressure-responsive base particles and fatty acid metal salt particles, in which the pressure-responsive base particles contain a styrene-based resin which contains styrene and other vinyl monomers as polymerization components and a (meth)acrylic acid ester-based resin which contains at least two kinds of (meth)acrylic acid esters as polymerization components and in which amass ratio of the (meth)acrylic acid esters to all polymerization components is 90% by mass or higher, the pressure-responsive particles have at least two glass transition temperatures, and a difference between the lowest glass transition temperature and the highest glass transition temperature is 30° C. or higher.Type: GrantFiled: January 15, 2021Date of Patent: April 23, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Yoshifumi Iida, Takashi Hasegawa, Satomi Kashiwagi, Takako Kobayashi, Satoshi Inoue
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Publication number: 20240110848Abstract: A misfire determination apparatus for an internal combustion engine including a rotational speed detector detecting a rotational speed of an engine and a microprocessor. The microprocessor is configured to perform calculating a misfire parameter having a correlation with a change amount of the rotational speed in a combustion stroke of each of a plurality of cylinders and increasing as an increase amount of the rotational speed is large based on the rotational speed detected by the rotational speed detector, and determining that a single-cylinder misfire has occurred when the misfire parameter is less than a first predetermined value, while determining that the single-cylinder misfire or a multi-cylinder misfire has occurred when the misfire parameter is less than a second predetermined value greater than the first predetermined value.Type: ApplicationFiled: September 26, 2023Publication date: April 4, 2024Inventors: Nobukazu Asano, Jun Iida, Satoshi Kozuka, Atsuhiro Miyauchi, Hayato Watanabe
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Publication number: 20230069864Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.Type: ApplicationFiled: August 24, 2022Publication date: March 9, 2023Inventors: Yuki MURAYAMA, Makoto KOSHIMIZU, Takahiro MORI, Junjiro SAKAI, Satoshi IIDA
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Patent number: 11289363Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.Type: GrantFiled: May 12, 2020Date of Patent: March 29, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shigeo Tokumitsu, Yoshiki Maruyama, Satoshi Iida
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Publication number: 20200411360Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.Type: ApplicationFiled: May 12, 2020Publication date: December 31, 2020Inventors: Shigeo TOKUMITSU, Yoshiki MARUYAMA, Satoshi IIDA
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Publication number: 20190297504Abstract: A terminal device configured to receive a remote data erasure service from a management device, includes a storage unit configured to store SIM information and unlock password information relating to a communication with the manager device; a lock control unit configured to lock the terminal device when the SIM information recognized by the terminal device is determined to be different from the stored SIM information by referring to the storage unit; a reception unit configured to receive an input of password information after the terminal device is locked; and a registration unit configured to register the recognized SIM information in the storage unit when the received password information is determined to be the same as the stored unlock password information.Type: ApplicationFiled: June 13, 2019Publication date: September 26, 2019Inventor: Satoshi IIDA
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Patent number: 9960075Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.Type: GrantFiled: April 26, 2017Date of Patent: May 1, 2018Assignee: Renesas Electronics CorporationInventors: Masaaki Shinohara, Satoshi Iida
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Patent number: 9903405Abstract: The bolt of the present invention can reliably peel coating even when fastened with a low torque, and can secure sufficient conductivity. A coating peeling part for peeling coating is formed at a tip end of an axis part in which a regular screw part is formed. The coating peeling part includes crushing parts having a trapezoidal top part and having a flank which is projected at a different angle with respect to the flank of the regular screw part; and a protruding part which is arranged adjacent to the crushing parts and whose top part projects beyond the outer diameter of the regular screw part.Type: GrantFiled: January 20, 2016Date of Patent: February 27, 2018Assignee: Aoyama Seisakusho Co., Ltd.Inventors: Yukinori Fujimoto, Kazuoki Shibuya, Satoshi Iida, Naoki Inaba, Yuki Nishimura, Kazuhiro Koga
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Patent number: 9831696Abstract: A power supply controller includes: a processor configured to control a power supply of an information processing apparatus having a plurality of batteries, wherein the processor determines residual capacities of the plurality of batteries and preferentially charges a first battery of the plurality of batteries, the first battery having a residual capacity which is equal to or below a transition-allowable residual capacity that allows a transition of the information processing apparatus from a first mode to a second mode.Type: GrantFiled: December 29, 2015Date of Patent: November 28, 2017Assignee: FUJITSU LIMITEDInventor: Satoshi Iida
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Publication number: 20170229338Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.Type: ApplicationFiled: April 26, 2017Publication date: August 10, 2017Inventors: Masaaki SHINOHARA, Satoshi IIDA
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Patent number: 9666584Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.Type: GrantFiled: July 22, 2016Date of Patent: May 30, 2017Assignee: Renesas Electronics CorporationInventors: Masaaki Shinohara, Satoshi Iida
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Publication number: 20160329330Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.Type: ApplicationFiled: July 22, 2016Publication date: November 10, 2016Inventors: Masaaki SHINOHARA, Satoshi IIDA
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Publication number: 20160291675Abstract: A power supply controller includes: a processor configured to control a power supply of an information processing apparatus having a plurality of batteries, wherein the processor determines residual capacities of the plurality of batteries and preferentially charges a first battery of the plurality of batteries, the first battery having a residual capacity which is equal to or below a transition-allowable residual capacity that allows a transition of the information processing apparatus from a first mode to a second mode.Type: ApplicationFiled: December 29, 2015Publication date: October 6, 2016Applicant: FUJITSU LIMITEDInventor: Satoshi IIDA
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Patent number: 9418996Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.Type: GrantFiled: February 25, 2016Date of Patent: August 16, 2016Assignee: Renesas Electronics CorporationInventors: Masaaki Shinohara, Satoshi Iida
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Publication number: 20160181246Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.Type: ApplicationFiled: February 25, 2016Publication date: June 23, 2016Inventors: Masaaki SHINOHARA, Satoshi IIDA
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Publication number: 20160138639Abstract: The bolt of the present invention can reliably peel coating even when fastened with a low torque, and can secure sufficient conductivity. A coating peeling part 4 for peeling coating is formed at a tip end of an axis part 2 in which a regular screw part 1 is formed. The coating peeling part 4 includes crushing parts 5 having a trapezoidal top part and having a flank which is projected at a different angle with respect to the flank of the regular screw part 1; and a protruding part 6 which is arranged adjacent to the crushing parts 5 and whose top part projects beyond the outer diameter of the regular screw part 1.Type: ApplicationFiled: January 20, 2016Publication date: May 19, 2016Inventors: Yukinori FUJIMOTO, Kazuoki SHIBUYA, Satoshi IIDA, Naoki INABA, Yuki NISHIMURA, Kazuhiro KOGA
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Patent number: 9305824Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.Type: GrantFiled: June 13, 2015Date of Patent: April 5, 2016Assignee: Renesas Electronics CorporationInventors: Masaaki Shinohara, Satoshi Iida
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Publication number: 20160005640Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.Type: ApplicationFiled: June 13, 2015Publication date: January 7, 2016Inventors: Masaaki Shinohara, Satoshi Iida
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Patent number: 9022710Abstract: Provided is a nut into which a bolt (10) including a male-threaded portion with a male-threaded external diameter d and a male-threaded core diameter d1 is screwed, wherein a bolt insertion side end of a female-threaded portion (21) formed in a nut body (20) is provided with an incompletely threaded female portion (22) that is formed by one to three pitches so that an internal diameter dimension D is larger than (d+d1)/2 and is smaller than the male-threaded external diameter d. Accordingly, even when the bolt is screwed into the nut in the inclination direction, the bolt may be rotated about a contact surface with respect to the incompletely threaded female portion (22), and hence seizing may be prevented.Type: GrantFiled: January 31, 2014Date of Patent: May 5, 2015Assignee: Aoyama Seisakusho Co., Ltd.Inventors: Satoshi Konagaya, Kenya Yamada, Sadayoshi Hasegawa, Satoshi Iida