Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.

Abstract: A terminal device configured to receive a remote data erasure service from a management device, includes a storage unit configured to store SIM information and unlock password information relating to a communication with the manager device; a lock control unit configured to lock the terminal device when the SIM information recognized by the terminal device is determined to be different from the stored SIM information by referring to the storage unit; a reception unit configured to receive an input of password information after the terminal device is locked; and a registration unit configured to register the recognized SIM information in the storage unit when the received password information is determined to be the same as the stored unlock password information.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: The bolt of the present invention can reliably peel coating even when fastened with a low torque, and can secure sufficient conductivity. A coating peeling part for peeling coating is formed at a tip end of an axis part in which a regular screw part is formed. The coating peeling part includes crushing parts having a trapezoidal top part and having a flank which is projected at a different angle with respect to the flank of the regular screw part; and a protruding part which is arranged adjacent to the crushing parts and whose top part projects beyond the outer diameter of the regular screw part.

Abstract: A power supply controller includes: a processor configured to control a power supply of an information processing apparatus having a plurality of batteries, wherein the processor determines residual capacities of the plurality of batteries and preferentially charges a first battery of the plurality of batteries, the first battery having a residual capacity which is equal to or below a transition-allowable residual capacity that allows a transition of the information processing apparatus from a first mode to a second mode.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: A power supply controller includes: a processor configured to control a power supply of an information processing apparatus having a plurality of batteries, wherein the processor determines residual capacities of the plurality of batteries and preferentially charges a first battery of the plurality of batteries, the first battery having a residual capacity which is equal to or below a transition-allowable residual capacity that allows a transition of the information processing apparatus from a first mode to a second mode.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: The bolt of the present invention can reliably peel coating even when fastened with a low torque, and can secure sufficient conductivity. A coating peeling part 4 for peeling coating is formed at a tip end of an axis part 2 in which a regular screw part 1 is formed. The coating peeling part 4 includes crushing parts 5 having a trapezoidal top part and having a flank which is projected at a different angle with respect to the flank of the regular screw part 1; and a protruding part 6 which is arranged adjacent to the crushing parts 5 and whose top part projects beyond the outer diameter of the regular screw part 1.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract: Provided is a nut into which a bolt (10) including a male-threaded portion with a male-threaded external diameter d and a male-threaded core diameter d1 is screwed, wherein a bolt insertion side end of a female-threaded portion (21) formed in a nut body (20) is provided with an incompletely threaded female portion (22) that is formed by one to three pitches so that an internal diameter dimension D is larger than (d+d1)/2 and is smaller than the male-threaded external diameter d. Accordingly, even when the bolt is screwed into the nut in the inclination direction, the bolt may be rotated about a contact surface with respect to the incompletely threaded female portion (22), and hence seizing may be prevented.

Abstract: Provided is a nut into which a bolt (10) including a male-threaded portion with a male-threaded external diameter d and a male-threaded core diameter d1 is screwed, wherein a bolt insertion side end of a female-threaded portion (21) formed in a nut body (20) is provided with an incompletely threaded female portion (22) that is formed by one to three pitches so that an internal diameter dimension D is larger than (d+d1)/2 and is smaller than the male-threaded external diameter d. Accordingly, even when the bolt is screwed into the nut in the inclination direction, the bolt may be rotated about a contact surface with respect to the incompletely threaded female portion (22), and hence seizing may be prevented.

Abstract: Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.