Patents by Inventor Satoshi Imasu
Satoshi Imasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11177790Abstract: An acoustic wave device includes: a piezoelectric substrate; and a pair of comb-shaped electrodes located on the piezoelectric substrate, each of the comb-shaped electrodes including a plurality of electrode fingers, side surfaces facing each other of the electrode fingers having a plurality of protrusion portions and a plurality of recessed portions arranged in an extension direction of the electrode fingers, ends of the protrusion portions and the recessed portions narrowing.Type: GrantFiled: October 10, 2019Date of Patent: November 16, 2021Assignee: TAIYO YUDEN CO., LTD.Inventors: Shinpei Miura, Satoshi Imasu, Masafumi Iwaki
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Patent number: 10938371Abstract: An acoustic wave resonator includes: an IDT located on a piezoelectric substrate, including comb-shaped electrodes facing each other and including electrode fingers and a bus bar connecting the electrode fingers; a first silicon oxide film located on the electrode fingers in an overlap region where the electrode fingers overlap and having a film thickness in a part of edge regions, which correspond to both ends of the overlap region, equal to or less than that in a center region sandwiched between the edge regions; and a second silicon oxide film located on the electrode fingers, containing an element slowing an acoustic velocity in a silicon oxide film when being added to the silicon oxide film, having a concentration of the element greater than that in the first silicon oxide film, and having a film thickness in a part of the edge regions greater than that in the center region.Type: GrantFiled: April 20, 2018Date of Patent: March 2, 2021Assignee: TAIYO YUDEN CO., LTD.Inventors: Kentaro Nakamura, Fumiya Matsukura, Satoshi Imasu, Takashi Matsuda
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Patent number: 10700662Abstract: An acoustic wave device includes: a piezoelectric substrate; and a pair of comb-shaped electrodes that is located on the piezoelectric substrate, includes a metal film, and excites a surface acoustic wave, the metal film being mainly composed of a metal having a melting point equal to or higher than a melting point of Pt, the metal film having a first region in which a crystal grain has a columnar shape and a second region that is located on and/or under the first region in a stacking direction and has less crystallinity than the first region or has an amorphous structure.Type: GrantFiled: November 21, 2018Date of Patent: June 30, 2020Assignee: TAIYO YUDEN CO., LTD.Inventors: Shinpei Miura, Satoshi Imasu, Takashi Matsuda, Masafumi Iwaki
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Publication number: 20200186123Abstract: An acoustic wave device includes: a piezoelectric substrate; and a pair of comb-shaped electrodes located on the piezoelectric substrate, each of the comb-shaped electrodes including a plurality of electrode fingers, side surfaces facing each other of the electrode fingers having a plurality of protrusion portions and a plurality of recessed portions arranged in an extension direction of the electrode fingers, ends of the protrusion portions and the recessed portions narrowing.Type: ApplicationFiled: October 10, 2019Publication date: June 11, 2020Applicant: TAIYO YUDEN CO., LTD.Inventors: Shinpei MIURA, Satoshi IMASU, Masafumi IWAKI
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Publication number: 20190207583Abstract: An acoustic wave device includes: a piezoelectric substrate; and a pair of comb-shaped electrodes that is located on the piezoelectric substrate, includes a metal film, and excites a surface acoustic wave, the metal film being mainly composed of a metal having a melting point equal to or higher than a melting point of Pt, the metal film having a first region in which a crystal grain has a columnar shape and a second region that is located on and/or under the first region in a stacking direction and has less crystallinity than the first region or has an amorphous structure.Type: ApplicationFiled: November 21, 2018Publication date: July 4, 2019Applicant: TAIYO YUDEN CO., LTD.Inventors: Shinpei MIURA, Satoshi IMASU, Takashi MATSUDA, Masafumi IWAKI
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Publication number: 20180316333Abstract: An acoustic wave resonator includes: an IDT located on a piezoelectric substrate, including comb-shaped electrodes facing each other and including electrode fingers and a bus bar connecting the electrode fingers; a first silicon oxide film located on the electrode fingers in an overlap region where the electrode fingers overlap and having a film thickness in a part of edge regions, which correspond to both ends of the overlap region, equal to or less than that in a center region sandwiched between the edge regions; and a second silicon oxide film located on the electrode fingers, containing an element slowing an acoustic velocity in a silicon oxide film when being added to the silicon oxide film, having a concentration of the element greater than that in the first silicon oxide film, and having a film thickness in a part of the edge regions greater than that in the center region.Type: ApplicationFiled: April 20, 2018Publication date: November 1, 2018Applicant: TAIYO YUDEN CO., LTD.Inventors: Kentaro NAKAMURA, Fumiya MATSUKURA, Satoshi IMASU, Takashi MATSUDA
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Patent number: 8101468Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: GrantFiled: October 18, 2010Date of Patent: January 24, 2012Assignee: Renesas Electronics CorporationInventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Publication number: 20110033983Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: ApplicationFiled: October 18, 2010Publication date: February 10, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Patent number: 7834455Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: GrantFiled: May 22, 2009Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Publication number: 20090230551Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: ApplicationFiled: May 22, 2009Publication date: September 17, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Patent number: 7547968Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2 , and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: GrantFiled: May 17, 2006Date of Patent: June 16, 2009Assignee: Renesas Technology Corp.Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Patent number: 7524697Abstract: A burn-in process for a semiconductor integrated circuit device includes a first process of positioning bump electrodes of the semiconductor integrated circuit device with respect to pads of a socket having detachment mechanisms, a second process of pressing the bump electrodes against the pads by weighting the semiconductor integrated circuit device, and a third process of detaching the bump electrodes from the pads by exerting force on the semiconductor integrated circuit device in a direction opposite to a weighting direction of the second process. Automatic insertion and detachment of a semiconductor integrated circuit chip in a burn-in test is facilitated by detaching the bump electrodes from the pads by pushing up the semiconductor integrated circuit device.Type: GrantFiled: January 18, 2005Date of Patent: April 28, 2009Assignee: Renesas Technology Corp.Inventors: Naohiro Makihira, Satoshi Imasu, Masanao Sato
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Patent number: 7365426Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.Type: GrantFiled: April 14, 2006Date of Patent: April 29, 2008Assignee: Renesas Technology Corp.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
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Publication number: 20070287206Abstract: A burn-in process for a semiconductor integrated circuit device includes a first process of positioning bump electrodes of the semiconductor integrated circuit device with respect to pads of a socket having detachment mechanisms, a second process of pressing the bump electrodes against the pads by weighting the semiconductor integrated circuit device, and a third process of detaching the bump electrodes from the pads by exerting force on the semiconductor integrated circuit device in a direction opposite to a weighting direction of the second process. Automatic insertion and detachment of a semiconductor integrated circuit chip in a burn-in test is facilitated by detaching the bump electrodes from the pads by pushing up the semiconductor integrated circuit device.Type: ApplicationFiled: January 18, 2005Publication date: December 13, 2007Inventors: Naohiro Makihara, Satoshi Imasu, Masanao Sato
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Publication number: 20060264022Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: ApplicationFiled: May 17, 2006Publication date: November 23, 2006Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Publication number: 20060197204Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.Type: ApplicationFiled: April 14, 2006Publication date: September 7, 2006Applicant: Hitachi,Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
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Patent number: 7057278Abstract: In a semiconductor device adapted to be mounted on a board and to be electrically connected to the board, comprising, at least two semiconductor electric chips, and a substrate on which the semiconductor electric chips are mounted and to which the semiconductor electric chips are electrically connected, in such a manner that the semiconductor electric chips are mounted on and electrically connected to the board through the substrate, according to the present invention, a thickness of each of the semiconductor electric chips in a direction in which the each of the semiconductor electric chips and the substrate are stacked is smaller than a thickness of the substrate in the direction.Type: GrantFiled: December 18, 2003Date of Patent: June 6, 2006Assignee: Hitachi, Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
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Publication number: 20050029673Abstract: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.Type: ApplicationFiled: September 14, 2004Publication date: February 10, 2005Applicant: Hitachi, Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
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Patent number: 6800945Abstract: In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.Type: GrantFiled: April 5, 2002Date of Patent: October 5, 2004Assignee: Hitachi, Ltd.Inventors: Yasuhiro Naka, Naotaka Tanaka, Ikuo Yoshida, Satoshi Imasu, Takahiro Naito
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Patent number: 6780677Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.Type: GrantFiled: August 21, 2002Date of Patent: August 24, 2004Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura