Patents by Inventor Satoshi Itaya

Satoshi Itaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111262
    Abstract: A system including control devices configured to perform nth-order transmission, each control device including: a storage device storing, in relation to the control devices, a source list being a list of the control devices to be passed through from a most upstream control device to the control device and a destination list being a list of the control devices to be passed through from the control device to a most downstream control device; and a processor performing processing including: when an update request including a first source list of a first control device is received, updating the source list using the update request, generating a new update request using the updated source list, and transmitting the new update request to a second control device; and when a completion response including a second destination list of the second control device is received, updating the destination list using the completion response.
    Type: Application
    Filed: June 21, 2023
    Publication date: April 4, 2024
    Applicant: Fujitsu Limited
    Inventors: Koki INOUE, Kenji TAKA, Takayoshi NAKAYAMA, Shinya FUKUZAKI, Satoshi ITAYA, Naofumi OTSUKI, Wataru FUKUMOTO, Tomomi USUI
  • Publication number: 20230350331
    Abstract: An image forming apparatus includes an operation panel including a display, a belt through which an image formed thereon is transferred to a sheet, a head configured to form an image on the belt, and a controller configured to control the head to form an image on the belt according to operation settings. The controller is configured to, upon receipt of an instruction to execute a first job, determine whether the job includes forming an image, upon determining that the first job includes forming an image, determine whether a first condition for executing an adjustment operation to adjust the settings is satisfied, upon determining that the first condition is satisfied, control the display to display a screen through which execution of the adjustment operation and a timing thereof can be selected, and execute the first job and/or the adjustment operation based on a selection made through the screen.
    Type: Application
    Filed: December 14, 2022
    Publication date: November 2, 2023
    Inventor: Satoshi ITAYA
  • Patent number: 11675301
    Abstract: According to one embodiment, an image forming apparatus includes a printer and a controller. The printer performs image formation on a sheet at a first speed relating to a speed of image formation or at a second speed slower than the first speed. The controller acquires information on deterioration of developer contained in an own apparatus, and controls the printer to perform image formation at the first speed when the information does not satisfy a predetermined condition indicating that the developer is deteriorated and to perform image formation at the second speed when the information satisfies the predetermined condition.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: June 13, 2023
    Assignee: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Kei Onishi, Satoshi Itaya
  • Publication number: 20220269203
    Abstract: According to one embodiment, an image forming apparatus includes a printer and a controller. The printer performs image formation on a sheet at a first speed relating to a speed of image formation or at a second speed slower than the first speed. The controller acquires information on deterioration of developer contained in an own apparatus, and controls the printer to perform image formation at the first speed when the information does not satisfy a predetermined condition indicating that the developer is deteriorated and to perform image formation at the second speed when the information satisfies the predetermined condition.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 25, 2022
    Inventors: Kei Onishi, Satoshi Itaya
  • Patent number: 11281143
    Abstract: According to one embodiment, an image forming apparatus includes a printer and a controller. The printer performs image formation on a sheet at a first speed relating to a speed of image formation or at a second speed slower than the first speed. The controller acquires information on deterioration of developer contained in an own apparatus, and controls the printer to perform image formation at the first speed when the information does not satisfy a predetermined condition indicating that the developer is deteriorated and to perform image formation at the second speed when the information satisfies the predetermined condition.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 22, 2022
    Assignee: TOSHIBA TEC KABUSHIKI KAISHA
    Inventors: Kei Onishi, Satoshi Itaya
  • Publication number: 20210072686
    Abstract: According to one embodiment, an image forming apparatus includes a printer and a controller. The printer performs image formation on a sheet at a first speed relating to a speed of image formation or at a second speed slower than the first speed. The controller acquires information on deterioration of developer contained in an own apparatus, and controls the printer to perform image formation at the first speed when the information does not satisfy a predetermined condition indicating that the developer is deteriorated and to perform image formation at the second speed when the information satisfies the predetermined condition.
    Type: Application
    Filed: September 9, 2019
    Publication date: March 11, 2021
    Inventors: Kei Onishi, Satoshi Itaya
  • Publication number: 20210072687
    Abstract: According to one embodiment, an image forming apparatus includes a printer and a controller. The printer performs image formation on a sheet at a first speed relating to a speed of image formation or at a second speed slower than the first speed. The controller acquires information on deterioration of developer contained in an own apparatus, and controls the printer to perform image formation at the first speed when the information does not satisfy a predetermined condition indicating that the developer is deteriorated and to perform image formation at the second speed when the information satisfies the predetermined condition.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 11, 2021
    Inventors: Kei Onishi, Satoshi Itaya
  • Publication number: 20190094800
    Abstract: In accordance with an embodiment, an image forming apparatus comprises a humidity sensor, a developing device, a supply device, an acquisition section, and a controller. The supply device supplies the developing device with the developer based on toner density sensor detecting the toner density and a detection result of the toner density sensor among the developer in the developing device. Based on the detection result of the humidity sensor and a time from the completion of a processing relating to image formation to the start of a processing relating to next image formation, the acquisition section acquires a charge level of the developer in the developing device. Based on a first charge level acquired by the acquisition section at a first time and a second charge level acquired by the acquisition section at a second time after the first time, the controller controls to discharge the toner.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Satoshi Itaya, Mitsutoshi Watanabe
  • Patent number: 9250584
    Abstract: A fixer includes a fixing belt configured to move around a center, a heating unit configured to induction-heat the fixing belt, a pressing member that presses an outer surface of the fixing belt, a resilient member disposed opposite to the pressing member across the fixing belt, and a heat generating member that is capable of being induction-heated and disposed along the inner surface of the fixing belt between a first position and a second position that is downstream with respect to the first position in a moving direction of the fixing belt. An upstream end portion of the resilient member in the moving direction is in contact with a third position of the fixing belt, and an angle formed with respect to the center by the second and third positions is equal to or smaller than 60°.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 2, 2016
    Assignees: Kabushiki Kaisha Toshiba, Toshiba TEC Kabushiki Kaisha
    Inventors: Yoshiaki Okano, Satoshi Itaya, Yoshiki Kogiso
  • Patent number: 8873987
    Abstract: An embodiment provides an image forming apparatus including: a job acquiring unit that acquires an image forming job that gives instructions for performing forming of an image; an image forming process control unit that controls performance of the image forming job that the job acquiring unit acquires; a temperature information acquiring unit that acquires information showing temperature of the heating rotary body; a determining unit that determines whether the temperature of the heating rotary body which is acquired by the temperature information acquiring unit is equal to or higher than a predetermined stand-by temperature set as a temperature in a stand-by state that stands by to perform the image forming process, when the image forming process is completed, based on the image forming job by the image forming process control unit; and a fixing device control unit.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: October 28, 2014
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventors: Taizo Nozawa, Yukio Futamata, Noboru Furuyama, Satoshi Itaya, Hiroshi Katakura, Setsuo Takada
  • Patent number: 8735288
    Abstract: A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.
    Type: Grant
    Filed: November 16, 2013
    Date of Patent: May 27, 2014
    Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
  • Publication number: 20140073127
    Abstract: A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.
    Type: Application
    Filed: November 16, 2013
    Publication date: March 13, 2014
    Applicant: Elpida Memory, Inc.
    Inventors: Satoshi Itaya, Kayoko SHIBATA, Shoji AZUMA, Akira IDE
  • Patent number: 8604621
    Abstract: A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
  • Publication number: 20130114223
    Abstract: A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.
    Type: Application
    Filed: May 3, 2012
    Publication date: May 9, 2013
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Satoshi ITAYA, Satoshi ISA, Mitsuaki KATAGIRI, Dai SASAKI
  • Patent number: 8378507
    Abstract: A wiring substrate and a semiconductor chip mounted on the wiring substrate are connected together via a bonding wire. The distance from each end of the semiconductor chip to a wire bond pad provided on the wiring substrate is smaller than the height of the semiconductor chip.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: February 19, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Satoshi Itaya, Dai Sasaki, Mitsuaki Katagirl
  • Patent number: 8350389
    Abstract: A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: January 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Satoshi Itaya, Kayoko Shibata, Shoji Azuma, Akira Ide
  • Publication number: 20120263487
    Abstract: The fixing device according to the embodiment includes a fixing member which is heated at predetermined temperature for a fixing, a press member which is configured to move relative to the fixing member and to contact with the fixing member so as to transport an image bearing medium by cooperating with the fixing member during a fixing, driving member which moves the fixing member and press member in a plurality of speeds including predetermined speed for during the fixing, pressure change member which is configured to change a pressure between the fixing member and the press member, and control member which controls the driving member and the pressure change member, when the fixing member and the press member are idle for fixing, to reduce the pressure and the speed of the fixing member and the press member compared with during the fixing.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 18, 2012
    Applicants: TOSHIBA TEC KABUSHIKI KAISHA, KABUSHIKI KAISHA TOSHIBA
    Inventor: Satoshi ITAYA
  • Patent number: 8243465
    Abstract: A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates 2a, 2b are on the upper surface of semiconductor chip 1. First additional wiring layer for power source 10d and first additional wiring layer for ground 10s formed on respective additional substrates 2a, 2b form prescribed conductive areas on semiconductor chip 1. First power source wiring 40C1d or first ground wiring 40C1s are interconnected through additional wiring layers 10d and 10s. Second power source wiring 40C2d and second ground wiring 40C2s, which is extended in the same direction as with DQ system signal wiring 40CDQ, forms a feedback current path. Second power source wiring 40C2d and second ground wiring 40C2s are disposed adjacent to DQ system signal wiring 40CDQ.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: August 14, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Satoshi Itaya, Satoshi Isa, Mitsuaki Katagiri, Dai Sasaki
  • Publication number: 20110311257
    Abstract: An embodiment provides an image forming apparatus including: a job acquiring unit that acquires an image forming job that gives instructions for performing forming of an image; an image forming process control unit that controls performance of the image forming job that the job acquiring unit acquires; a temperature information acquiring unit that acquires information showing temperature of the heating rotary body; a determining unit that determines whether the temperature of the heating rotary body which is acquired by the temperature information acquiring unit is equal to or higher than a predetermined stand-by temperature set as a temperature in a stand-by state that stands by to perform the image forming process, when the image forming process is completed, based on the image forming job by the image forming process control unit; and a fixing device control unit, which controls the fixing device, performs a first stand-by control process that increases the temperature of the heating rotary body to the sta
    Type: Application
    Filed: June 20, 2011
    Publication date: December 22, 2011
    Applicants: TOSHIBA TEC KABUSHIKI KAISHA, KABUSHIKI KAISHA TOSHIBA
    Inventors: Taizo Nozawa, Yukio Futamata, Noboru Furuyama, Satoshi Itaya, Hiroshi Katakura, Setsuo Takada
  • Patent number: 7962074
    Abstract: A suction duct that sucks air is provided downstream from a magnet roller that applies a developer to a photoconductor while rotating, in a direction of rotation of the photoconductor, and upstream of a surface potential sensor that measures surface potential of the photoconductor. Moreover, ribs for adjusting an air flow are arranged within the suction duct in such a manner that a width of an air flow passage formed by a rear end in a direction of air flow and a forward end of a nearest rib in the direction of air flow is narrowed from a rib installed upstream in the direction of air flow toward a rib installed downstream. The collection duct collects a floating developer by using a negative pressure.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: June 14, 2011
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
    Inventors: Hirotaka Fukuyama, Satoshi Itaya