Patents by Inventor Satoshi Iwahashi
Satoshi Iwahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230253473Abstract: A method of manufacturing a semiconductor device having a super junction structure, includes: forming a first-conductivity-type semiconductor layer having a first surface and a second surface opposite to the first surface; forming a second-conductivity-type pillar region in the semiconductor layer; forming an insulating layer which covers the second surface of the semiconductor layer; forming a metal layer on the insulating layer; forming a gate electrode including a first opening passing through the metal layer by selectively removing the metal layer; and etching the insulating layer via the first opening, wherein the etching the insulating layer includes partially exposing the semiconductor layer by forming a second opening having a curved sidewall in the insulating layer by isotropic etching, and wherein an exposed surface of the semiconductor layer forms a flat surface continuous with the second surface of the semiconductor layer covered with the insulating layer.Type: ApplicationFiled: January 5, 2023Publication date: August 10, 2023Applicant: ROHM CO., LTD.Inventors: So NAGAKURA, Jun KOBAYASHI, Satoshi IWAHASHI, Kazuyoshi MAKI, Shu NAKASHIMA
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Publication number: 20230246105Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.Type: ApplicationFiled: March 28, 2023Publication date: August 3, 2023Inventors: So NAGAKURA, Satoshi IWAHASHI
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Patent number: 11646370Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.Type: GrantFiled: November 12, 2021Date of Patent: May 9, 2023Assignee: ROHM CO., LTD.Inventors: So Nagakura, Satoshi Iwahashi
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Publication number: 20220069121Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.Type: ApplicationFiled: November 12, 2021Publication date: March 3, 2022Inventors: So NAGAKURA, Satoshi IWAHASHI
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Patent number: 11205720Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.Type: GrantFiled: May 28, 2020Date of Patent: December 21, 2021Assignee: ROHM CO., LTD.Inventors: So Nagakura, Satoshi Iwahashi
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Publication number: 20200381551Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.Type: ApplicationFiled: May 28, 2020Publication date: December 3, 2020Inventors: So NAGAKURA, Satoshi IWAHASHI
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Patent number: 7012848Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: GrantFiled: August 13, 2004Date of Patent: March 14, 2006Assignee: Renesas Technology CorporationInventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
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Patent number: 7009862Abstract: Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.Type: GrantFiled: December 15, 2004Date of Patent: March 7, 2006Assignee: Hitachi, Ltd.Inventors: Keiichi Higeta, Satoshi Iwahashi, Yoichiro Aihara, Shigeru Nakahara
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Publication number: 20050146947Abstract: Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.Type: ApplicationFiled: December 15, 2004Publication date: July 7, 2005Inventors: Keiichi Higeta, Satoshi Iwahashi, Yoichiro Aihara, Shigeru Nakahara
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Patent number: 6856574Abstract: A semiconductor memory device comprises a memory-cell array for storing data, a peripheral circuit for carrying out an operation to read out or write data from or into the memory-cell array, read clock generation circuits (111, 113 and 115) each used for generating a read clock signal to be supplied to the peripheral circuit in the operation to read out data from the memory-cell array, write clock generation circuits (112, 114 and 116) each used for generating a write clock signal to be supplied to the peripheral circuit in the operation to write data into the memory-cell array. Since the pulse widths of the clock signals in read and writes are adjusted individually, margin insufficiencies of the pulse widths can be evaluated and results of the evaluation can be fed back to a design phase for, among other purposes, correction of a layout.Type: GrantFiled: November 25, 2003Date of Patent: February 15, 2005Assignee: Hitachi, Ltd.Inventors: Satoshi Iwahashi, Keiichi Higeta
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Publication number: 20050013159Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: ApplicationFiled: August 13, 2004Publication date: January 20, 2005Inventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
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Patent number: 6826109Abstract: The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.Type: GrantFiled: January 16, 2003Date of Patent: November 30, 2004Assignee: Hitachi, Ltd.Inventors: Shigeru Nakahara, Satoshi Iwahashi, Takeshi Suzuki, Keiichi Higeta, Kazuo Kanetani
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Patent number: 6795368Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: GrantFiled: December 15, 2003Date of Patent: September 21, 2004Assignee: Renesas Technology Corp.Inventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
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Publication number: 20040125683Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: ApplicationFiled: December 15, 2003Publication date: July 1, 2004Applicant: Renesas Technology CorporationInventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Hegeta
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Publication number: 20040105339Abstract: A semiconductor memory device comprises a memory-cell array for storing data, a peripheral circuit for carrying out an operation to read out or write data from or into the memory-cell array, read clock generation circuits (111, 113 and 115) each used for generating a read clock signal to be supplied to the peripheral circuit in the operation to read out data from the memory-cell array, write clock generation circuits (112, 114 and 116) each used for generating a write clock signal to be supplied to the peripheral circuit in the operation to write data into the memory-cell array. Since the pulse widths of the clock signals in read and writes are adjusted individually, margin insufficiencies of the pulse widths can be evaluated and results of the evaluation can be fed back to a design phase for, among other purposes, correction of a layout.Type: ApplicationFiled: November 25, 2003Publication date: June 3, 2004Inventors: Satoshi Iwahashi, Keiichi Higeta
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Patent number: 6707751Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: GrantFiled: January 10, 2003Date of Patent: March 16, 2004Assignee: Renesas Technology CorporationInventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
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Publication number: 20030142576Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: ApplicationFiled: January 10, 2003Publication date: July 31, 2003Applicant: Hitachi, ltd.Inventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
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Publication number: 20030142526Abstract: The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.Type: ApplicationFiled: January 16, 2003Publication date: July 31, 2003Applicant: Hitachi, Ltd.Inventors: Shigeru Nakahara, Satoshi Iwahashi, Takeshi Suzuki, Keiichi Higeta, Kazuo Kanetani