Abstract: A memory system is connectable to a host having a host memory and includes a non-volatile memory that stores management data, a memory controller configured to manage caching of parts of the management data in cache lines of the host memory, and a first memory configured to store a bitmap that includes a bit indicating whether the memory controller has accessed first data stored in the host memory after power was last supplied to the memory system. The first data indicates whether or not a part of the management data corresponding thereto is stored in one of the cache lines, and the memory controller is configured to perform either a first operation of reading the first data from the host memory or a second operation of reading an initial value of the first data managed by the memory controller, based on the bitmap.

Abstract: A memory system is connectable to the host. The memory system includes a nonvolatile first memory, a second memory in which a plurality of pieces of first information each correlating a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory are stored, a volatile third memory including a first cache and a second cache, a compressor configured to perform compression on the plurality of pieces of first information, and a memory controller. The memory controller stores the first information not compressed by the compressor in the first cache, stores the first information compressed by the compressor in the second cache, and controls a ratio between a first capacity, which is a capacity of the first cache, and a second capacity, which is a capacity of the second cache.

Abstract: A memory system is connectable to the host. The memory system includes a nonvolatile first memory, a second memory in which a plurality of pieces of first information each correlating a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory are stored, a volatile third memory including a first cache and a second cache, a compressor configured to perform compression on the plurality of pieces of first information, and a memory controller. The memory controller stores the first information not compressed by the compressor in the first cache, stores the first information compressed by the compressor in the second cache, and controls a ratio between a first capacity, which is a capacity of the first cache, and a second capacity, which is a capacity of the second cache.

Abstract: A first memory stores a translation table indicating a first correspondence between a logical address and a physical address at first timing. A second memory stores a difference table that is configured to record, in each of entries, a correspondence between a logical address range and a physical address range, the correspondence representing a difference between the first correspondence and a second correspondence. The second correspondence is between the logical address and the physical address at second timing. In non-volatilizing data in a first logical address range to a first physical address range, in a case where the entries includes a first entry containing a correspondence between a second logical address range and a second physical address range, the controller updates the first entry. The first logical address range follows the second logical address range, and the first physical address range follows the second physical address range.

Abstract: A memory system includes: a non-volatile first memory; a second memory which is a set-associative cache memory including a plurality of ways; and a memory controller The first memory stores a plurality of pieces of first information each of which associates a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory. The plurality of pieces of first information includes second information and third information. The second information associates a logical address with a physical address in a first unit. The third information associates a logical address with a physical address in a second unit different from the first unit. The memory controller caches the second information only in a first way. The memory controller caches the third information only in a second way different from the first way.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory using first data. The controller is configured to write either the first data or second data into the nonvolatile memory based on a total write amount of user data into the nonvolatile memory. The second data is compressed data of the first data.

Abstract: A first memory stores a translation table indicating a first correspondence between a logical address and a physical address at first timing. A second memory stores a difference table that is configured to record, in each of entries, a correspondence between a logical address range and a physical address range, the correspondence representing a difference between the first correspondence and a second correspondence. The second correspondence is between the logical address and the physical address at second timing. In non-volatilizing data in a first logical address range to a first physical address range, in a case where the entries includes a first entry containing a correspondence between a second logical address range and a second physical address range, the controller updates the first entry. The first logical address range follows the second logical address range, and the first physical address range follows the second physical address range.

Abstract: A memory system includes a memory controller and a memory that is nonvolatile. The memory controller divides first information, which correlates a logical address with a physical address of the memory, into multiple pieces of second information, attaches metadata to each of the multiple pieces of second information and stores each piece of second information with the attached metadata, into the memory, when using third information, which is one of the multiple pieces of second information, reads, as multiple pieces of fourth information, pieces of second information including the third information, from among the multiple pieces of second information stored in the memory, selects fifth information, which is different from the third information, from among the read multiple pieces of fourth information based on the metadata attached to each of the multiple pieces of fourth information, and caches the selected fifth information into another memory.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.

Abstract: According to one embodiment, a part of first information stored in a nonvolatile second memory is cached in a volatile third memory with a first cache line size in a case where a first memory included in a host is not used. A part of the first information is cached in the first memory with a second cache line size in a case where the first memory is used. The second cache line size is larger than the first cache line size.

Abstract: A memory system includes a memory controller and a memory that is nonvolatile. The memory controller divides first information, which correlates a logical address with a physical address of the memory, into multiple pieces of second information, attaches metadata to each of the multiple pieces of second information and stores each piece of second information with the attached metadata, into the memory, when using third information, which is one of the multiple pieces of second information, reads, as multiple pieces of fourth information, pieces of second information including the third information, from among the multiple pieces of second information stored in the memory, selects fifth information, which is different from the third information, from among the read multiple pieces of fourth information based on the metadata attached to each of the multiple pieces of fourth information, and caches the selected fifth information into another memory.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory using first data. The controller is configured to write either the first data or second data into the nonvolatile memory based on a total write amount of user data into the nonvolatile memory. The second data is compressed data of the first data.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a device controller, and a tag memory. The device controller stores a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of a host as a cache. The tag memory includes a plurality of entries associated with a plurality of cache lines of the cache. Each entry includes a tag indicating which area of the L2P table is stored in a corresponding cache line, and a plurality of bitmap flags indicating whether a plurality of sub-lines included in the corresponding cache line are valid or not.

Abstract: According to one embodiment, a memory controller includes a first volatile memory, a second volatile memory, and a controller. The first volatile memory temporarily stores therein data acquired from outside. The controller controls the temporarily stored data to be transferred from the first volatile memory to a non-volatile memory, stores correspondence information of the transferred data to the non-volatile memory in the second volatile memory, and updates correspondence information stored in the non-volatile memory based on the correspondence information stored in the second volatile memory by using the first volatile memory after the data transfer as a work area. The correspondence information represents association between a logical address and a physical address of the data.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory stores a multilevel address translation table including at least hierarchical first and second tables. The controller translates a logical address into a physical address by accessing a cache configured to cache both the first and second tables. The access range covered by each data portion of the second table is wider than the access range covered by each data portion of the first table. The controller preferentially evicts, from the cache, one of the cache lines which store the respective data portions of the first table.

Abstract: According to one embodiment, a part of first information stored in a nonvolatile second memory is cached in a volatile third memory with a first cache line size in a case where a first memory included in a host is not used. A part of the first information is cached in the first memory with a second cache line size in a case where the first memory is used. The second cache line size is larger than the first cache line size.

Abstract: According to one embodiment, a memory controller includes a first volatile memory, a second volatile memory, and a controller. The first volatile memory temporarily stores therein data acquired from outside. The controller controls the temporarily stored data to be transferred from the first volatile memory to a non-volatile memory, stores correspondence information of the transferred data to the non-volatile memory in the second volatile memory, and updates correspondence information stored in the non-volatile memory based on the correspondence information stored in the second volatile memory by using the first volatile memory after the data transfer as a work area. The correspondence information represents association between a logical address and a physical address of the data.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a device controller, and a tag memory. The device controller stores a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of a host as a cache. The tag memory includes a plurality of entries associated with a plurality of cache lines of the cache. Each entry includes a tag indicating which area of the L2P table is stored in a corresponding cache line, and a plurality of bitmap flags indicating whether a plurality of sub-lines included in the corresponding cache line are valid or not.

Abstract: According to one embodiment, an information processing apparatus includes a host and a memory system. The memory system includes a nonvolatile memory. The host includes a volatile memory, a first host control unit, and a second host control unit. The volatile memory includes a first area to be used by the host and a second area as a cache memory to temporarily store data of the nonvolatile memory. The first host control unit computes a first code, and stores the first data and the first code in the second area. The first code is redundant information of the first data. The second host control unit reads second data and a second code from the second area, performs error detection on the second data based on the second code, and transfers the second data. The second code is redundant information of the second data.