Patents by Inventor Satoshi Kageyama

Satoshi Kageyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12023940
    Abstract: A thermal print head includes a head substrate (11) having a main surface (11a) on which a convex part (12) is formed, a resistor layer (21) that is formed on the main surface (11a) and the convex part (12), a wiring layer (22) that covers the resistor layer (21) such that the resistor layer (21) is exposed at a heat generating part (20) formed at a part of the convex part (12), and a protective layer (25) that is formed on the main surface (11a) of the head substrate (11) and covers the resistor layer (21) and the wiring layer (22). The resistor layer (21) has a main resistor layer that contains tantalum, and at least one of a first sub-resistor layer that contains tantalum nitride and is stacked below the tantalum layer and a second sub-resistor layer that contains tantalum nitride and is stacked on the tantalum layer.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: July 2, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Satoshi Kageyama
  • Publication number: 20240014159
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Application
    Filed: September 21, 2023
    Publication date: January 11, 2024
    Applicant: ROHM CO., LTD.
    Inventors: Bungo TANAKA, Keiji WADA, Satoshi KAGEYAMA
  • Patent number: 11810881
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: November 7, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
  • Publication number: 20230298805
    Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.
    Type: Application
    Filed: April 13, 2023
    Publication date: September 21, 2023
    Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
  • Patent number: 11764130
    Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: September 19, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Satoshi Kageyama, Yoshihisa Takada
  • Patent number: 11657953
    Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: May 23, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
  • Publication number: 20230102799
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: March 30, 2023
    Inventors: Bungo TANAKA, Keiji WADA, Satoshi KAGEYAMA
  • Publication number: 20230091632
    Abstract: A semiconductor device includes: a resin layer having a resin main surface; a mounting wiring layer arranged on the resin main surface, and having a mounting wiring main surface facing the same side as the resin main surface and a mounting wiring back surface facing the side of the resin main surface; a semiconductor element including an element wiring layer which is mounted on the mounting wiring main surface, has an element wiring main surface facing the side of the resin layer, and is connected to the mounting wiring layer; and a sealing resin which seals the mounting wiring layer and the semiconductor element, wherein the mounting wiring main surface and the element wiring main surface are rough surfaces having a larger surface roughness than the mounting wiring back surface.
    Type: Application
    Filed: August 2, 2022
    Publication date: March 23, 2023
    Inventors: Satoshi KAGEYAMA, Hiroyuki SHINKAI, Yoshihisa TAKADA, Natsuki SAKAMOTO
  • Publication number: 20230092639
    Abstract: A semiconductor device includes: a conductive portion; and a semiconductor element mounted on the conductive portion, wherein the conductive portion is made of a plating layer, wherein the conductive portion includes a mounting portion having a mounting surface on which the semiconductor element is mounted, and a terminal portion extending to an opposite side of the semiconductor element with respect to the mounting portion, wherein the mounting portion extends in a first direction along the mounting surface more than the terminal portion, and wherein the mounting portion and the terminal portion are integrally formed.
    Type: Application
    Filed: August 17, 2022
    Publication date: March 23, 2023
    Inventor: Satoshi KAGEYAMA
  • Publication number: 20230036070
    Abstract: A thermal print head includes a head substrate (11) having a main surface (11a) on which a convex part (12) is formed, a resistor layer (21) that is formed on the main surface (11a) and the convex part (12), a wiring layer (22) that covers the resistor layer (21) such that the resistor layer (21) is exposed at a heat generating part (20) formed at a part of the convex part (12), and a protective layer (25) that is formed on the main surface (11a) of the head substrate (11) and covers the resistor layer (21) and the wiring layer (22). The resistor layer (21) has a main resistor layer that contains tantalum, and at least one of a first sub-resistor layer that contains tantalum nitride and is stacked below the tantalum layer and a second sub-resistor layer that contains tantalum nitride and is stacked on the tantalum layer.
    Type: Application
    Filed: October 6, 2022
    Publication date: February 2, 2023
    Applicant: ROHM CO., LTD.
    Inventor: Satoshi KAGEYAMA
  • Patent number: 11545454
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 3, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
  • Publication number: 20220173017
    Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.
    Type: Application
    Filed: February 18, 2022
    Publication date: June 2, 2022
    Inventors: Satoshi Kageyama, Yoshihisa Takada
  • Publication number: 20220139815
    Abstract: The present disclosure relates to a semiconductor device and a method manufacturing thereof. The object of the present disclosure is to simplify manufacturing steps of a semiconductor device. A semiconductor device of the present disclosure includes an organic film electrically insulative and penetrated by a through hole in a thickness direction, a conductive layer formed on the organic film and made of a copper (Cu)-based and titanium (Ti)-free alloy, a Cu wiring layer formed on the conductive layer, a semiconductor element mounted on the Cu wiring layer, a sealing resin sealing the semiconductor element, and an external terminal connected to the conductive layer. The conductive layer includes the exposed conductive portion exposed from the organic film by entering the through hole. The external terminal is in contact with the exposed conductive portion.
    Type: Application
    Filed: October 26, 2021
    Publication date: May 5, 2022
    Inventor: Satoshi KAGEYAMA
  • Patent number: 11289405
    Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 29, 2022
    Assignee: ROHM Co., Ltd.
    Inventors: Satoshi Kageyama, Yoshihisa Takada
  • Publication number: 20210233882
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Inventors: Bungo TANAKA, Keiji WADA, Satoshi KAGEYAMA
  • Publication number: 20210233700
    Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Inventors: Kosei OSADA, Isamu NISHIMURA, Tetsuya KAGAWA, Daiki YANAGISHIMA, Toshiyuki ISHIKAWA, Michihiko MIFUJI, Satoshi KAGEYAMA, Nobuyuki KASAHARA
  • Patent number: 11011489
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: May 18, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
  • Patent number: 11011297
    Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: May 18, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Kosei Osada, Isamu Nishimura, Tetsuya Kagawa, Daiki Yanagishima, Toshiyuki Ishikawa, Michihiko Mifuji, Satoshi Kageyama, Nobuyuki Kasahara
  • Publication number: 20210035889
    Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.
    Type: Application
    Filed: July 27, 2020
    Publication date: February 4, 2021
    Inventors: Satoshi KAGEYAMA, Yoshihisa TAKADA
  • Publication number: 20200235064
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Bungo TANAKA, Keiji WADA, Satoshi KAGEYAMA