Patents by Inventor Satoshi Kameda

Satoshi Kameda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240159158
    Abstract: A shroud of a vane of a turbine is provided. The shroud includes a shroud main body comprising a first wall having a gas-passage face facing a hot gas passage of the turbine and a cooling face facing opposite to the hot gas passage, a shroud edge disposed on a circumference of the shroud main body to surround the shroud main body, the shroud edge comprising a shroud edge passage therein, and an impingement box disposed to face the cooling face of the first wall so as to be spaced apart from the cooling face of the first wall. The impingement box comprises a cooling air inlet to introduce a cooling air from the shroud edge passage into an inside of the impingement box, and an impingement air hole configured to jet the introduced cooling air to the cooling face of the first wall to cool the cooling face of the first wall.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Satoshi Mizukami, David Allen Flodman, Satoshi Hada, Yasumasa Kunisada, Saki Matsuo, Ryo Tanaka, Takuro Kameda, Yusuke Akada
  • Patent number: 11936044
    Abstract: A carbon material for a non-aqueous secondary battery containing a graphite capable of occluding and releasing lithium ions, and having a cumulative pore volume at pore diameters in a range of 0.01 ?m to 1 ?m of 0.08 mL/g or more, a roundness, as determined by flow-type particle image analysis, of 0.88 or greater, and a pore diameter to particle diameter ratio (PD/d50 (%)) of 1.8 or less, the ratio being given by equation (1A): PD/d50 (%)=mode pore diameter (PD) in a pore diameter range of 0.01 ?m to 1 ?m in a pore distribution determined by mercury intrusion/volume-based average particle diameter (d50)×100 is provided.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: March 19, 2024
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Shunsuke Yamada, Nobuyuki Ishiwatari, Satoshi Akasaka, Daigo Nagayama, Shingo Morokuma, Koichi Nishio, Iwao Soga, Hideaki Tanaka, Takashi Kameda, Tooru Fuse, Hiromitsu Ikeda
  • Patent number: 8581639
    Abstract: A differential output circuit is controlled according to its mode of operation. While in the first mode, the differential output circuit controls a current flow through a variable current source according to an impedance of the variable current source, and while in the second mode, the differential output circuit compares a voltage at a monitored node and a reference voltage and controls the current flow through the variable current source to make the voltage at the monitored node to be equal to the reference voltage.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Kameda, Takuma Aoyama
  • Publication number: 20130162318
    Abstract: A differential output circuit is controlled according to its mode of operation. While in the first mode, the differential output circuit controls a current flow through a variable current source according to an impedance of the variable current source, and while in the second mode, the differential output circuit compares a voltage at a monitored node and a reference voltage and controls the current flow through the variable current source to make the voltage at the monitored node to be equal to the reference voltage.
    Type: Application
    Filed: September 7, 2012
    Publication date: June 27, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi KAMEDA, Takuma AOYAMA
  • Patent number: 7945826
    Abstract: Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: May 17, 2011
    Assignee: Advantest Corporation
    Inventors: Satoshi Kameda, Masaru Doi, Shinya Sato
  • Publication number: 20090327822
    Abstract: Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information.
    Type: Application
    Filed: June 18, 2009
    Publication date: December 31, 2009
    Applicant: ADVANTEST CORPORATION
    Inventors: Satoshi KAMEDA, Masaru DOI, Shinya SATO