Patents by Inventor Satoshi Kamiya

Satoshi Kamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982539
    Abstract: A display system applied to a vehicle includes a navigation device guiding a route to a destination and a display control device displaying multiple route guidance contents in superimposed manner on a road surface using a head-up display. When the navigation device determines that a first route guidance and a second route guidance included in route guidance information are successive guidance, (i) the navigation device concurrently displays images of the first route guidance and the second route guidance, and (ii) the display control device activates display of a first guidance content that performs the first route guidance, and then activates display of a second guidance content that performs the second route guidance after deactivating the display of the first guidance content.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: May 14, 2024
    Assignee: DENSO CORPORATION
    Inventors: Satoshi Horihata, Kazuki Kojima, Akira Kamiya, Motohiro Fukumoto, Takeshi Hato
  • Publication number: 20240096653
    Abstract: According to one embodiment a substrate treatment apparatus incorporates, into a frozen film, a contaminant adhered to a substrate surface by freezing a liquid film on the surface. The apparatus includes a placement part configured to rotate the substrate, a liquid supply part configured to supply a liquid via a nozzle to the frozen film including the contaminant, a moving part configured to move the nozzle parallel to the substrate surface, and a controller configured to control a rotation of the substrate by the placement part, a supply of the liquid by the liquid supply part, and a movement of the nozzle by the moving part. The controller rotates the substrate by controlling the placement part, supplies the liquid to the frozen film by controlling the liquid supply part, and moves the nozzle from a perimeter edge vicinity to a rotation center vicinity of the substrate by controlling the moving part.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 21, 2024
    Inventors: Kensuke DEMURA, Satoshi NAKAMURA, Masaya KAMIYA, Minami NAKAMURA, Kosuke TAKAI, Mana TANABE, Kaori UMEZAWA
  • Patent number: 11914317
    Abstract: An image forming apparatus includes a photosensitive drum, a developing device configured to supply toner onto the photosensitive drum, a transfer device configured to transfer the toner supplied onto the photosensitive drum onto a sheet, a spraying device configured to spray a fixing liquid toward the sheet onto which the toner has been transferred, the spraying device including a housing configured to accommodate the fixing liquid and nozzles configured to spray the fixing liquid inside the housing, and a collecting device configured to collect the fixing liquid sprayed from the nozzles and did not adhere to the sheet. The collecting device includes a collection tray configured to accommodate the fixing liquid, a collection pipe connected to the collection tray and configured to allow the fixing liquid in the collection tray to pass therethrough, and a collection pump configured to send the fixing liquid in the collection pipe toward the housing.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: February 27, 2024
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Masataka Kamiya, Yutaka Kakigahara, Satoshi Murata, Takashi Shimizu, Koya Morimoto, Masamitsu Takahashi
  • Patent number: 11739789
    Abstract: Provided is a half bearing constituting a sliding bearing that is unlikely to cause damage during an operation of an internal combustion engine. The half bearing includes at least one protrusion, and the protrusion projects outward in a radial direction from an outer circumferential surface. A recessed portion that is recessed inward in the radial direction from the outer circumferential surface is formed over the entire inner-circumferential length between the protrusion and a circumferential-direction end surface of the half bearing. Two radial-direction grooves are formed in the circumferential-direction end surface of the half bearing relative to the protrusion, and each of the radial-direction grooves is adjacent to each of recessed portion side surfaces. The radial-direction grooves extend in the radial direction along the recessed portion side surfaces and are separated from the recessed portion at a midpoint of the extension.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: August 29, 2023
    Assignee: DAIDO METAL COMPANY LTD.
    Inventors: Keisuke Shinoda, Tomohiro Yamada, Satoshi Kamiya
  • Publication number: 20230069203
    Abstract: Provided is a half bearing constituting a sliding bearing that is unlikely to cause damage during an operation of an internal combustion engine. The half bearing includes at least one protrusion, and the protrusion projects outward in a radial direction from an outer circumferential surface. A recessed portion that is recessed inward in the radial direction from the outer circumferential surface is formed over the entire inner-circumferential length between the protrusion and a circumferential-direction end surface of the half bearing. Two radial-direction grooves are formed in the circumferential-direction end surface of the half bearing relative to the protrusion, and each of the radial-direction grooves is adjacent to each of recessed portion side surfaces. The radial-direction grooves extend in the radial direction along the recessed portion side surfaces and are separated from the recessed portion at a midpoint of the extension.
    Type: Application
    Filed: August 8, 2022
    Publication date: March 2, 2023
    Inventors: Keisuke SHINODA, Tomohiro YAMADA, Satoshi KAMIYA
  • Patent number: 11588475
    Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: February 21, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Haruya Iwata, Tatsuya Tokue, Sohei Kushida, Takayuki Mori, Satoshi Kamiya
  • Patent number: 11522541
    Abstract: A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: December 6, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Joi Okugi, Daisuke Katori, Satoru Suzuki, Satoshi Kamiya
  • Publication number: 20220085807
    Abstract: A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 17, 2022
    Inventors: Joi Okugi, Daisuke Katori, Satoru Suzuki, Satoshi Kamiya
  • Publication number: 20220029612
    Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.
    Type: Application
    Filed: October 13, 2021
    Publication date: January 27, 2022
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Haruya IWATA, Tatsuya TOKUE, Sohei KUSHIDA, Takayuki MORI, Satoshi KAMIYA
  • Patent number: 11177798
    Abstract: According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: November 16, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Haruya Iwata, Tatsuya Tokue, Sohei Kushida, Takayuki Mori, Satoshi Kamiya
  • Publication number: 20210091756
    Abstract: According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.
    Type: Application
    Filed: August 11, 2020
    Publication date: March 25, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Haruya IWATA, Tatsuya TOKUE, Sohei KUSHIDA, Takayuki MORI, Satoshi KAMIYA
  • Publication number: 20210089213
    Abstract: An information processing apparatus comprises a central processor, a volatile memory, a non-volatile memory, a backup line, and a controller. The volatile memory is configured in such a manner that data is input and output thereto and therefrom via a bus under control of the central processor. The non-volatile memory is configured in such a manner that data is input and output thereto and therefrom via the bus under control of the central processor. The backup line is provided between the volatile memory and the non-volatile memory. The controller is configured to control data transfer performed between the volatile memory and the non-volatile memory via the backup line in a transition period between a normal mode of supplying normal power to the volatile memory and a low power consumption mode of reducing or interrupting normal power to be supplied to the volatile memory.
    Type: Application
    Filed: March 3, 2020
    Publication date: March 25, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Sohei KUSHIDA, Tatsuya TOKUE, Haruya IWATA, Satoshi KAMIYA, Takayuki MORI
  • Publication number: 20200301464
    Abstract: A semiconductor device of an embodiment includes a path monitor circuit provided in a predetermined data path in a circuit that operates with a predetermined source clock, the path monitor circuit being configured to generate an output corresponding to a degree of a timing margin, a power supply voltage control circuit configured to set a power supply voltage that is used in the circuit based on an output of the path monitor circuit, and a clock generating circuit configured to supply to the circuit a clock obtained by dividing a frequency of the source clock, based on a detection result indicating that the power supply voltage obtained based on the output of the path monitor circuit becomes lower than a predetermined threshold.
    Type: Application
    Filed: September 5, 2019
    Publication date: September 24, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Satoshi KAMIYA, Tatsuya TOKUE
  • Patent number: 10775831
    Abstract: A semiconductor device of an embodiment includes a path monitor circuit provided in a predetermined data path in a circuit that operates with a predetermined source clock, the path monitor circuit being configured to generate an output corresponding to a degree of a timing margin, a power supply voltage control circuit configured to set a power supply voltage that is used in the circuit based on an output of the path monitor circuit, and a clock generating circuit configured to supply to the circuit a clock obtained by dividing a frequency of the source clock, based on a detection result indicating that the power supply voltage obtained based on the output of the path monitor circuit becomes lower than a predetermined threshold.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 15, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Satoshi Kamiya, Tatsuya Tokue
  • Patent number: 10712767
    Abstract: According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: July 14, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Satoshi Kamiya
  • Patent number: 10460772
    Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 29, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takayuki Mori, Tatsuya Tokue, Haruya Iwata, Sohei Kushida, Satoshi Kamiya
  • Publication number: 20190287577
    Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 19, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takayuki MORI, Tatsuya TOKUE, Haruya IWATA, Sohei KUSHIDA, Satoshi KAMIYA
  • Publication number: 20190086949
    Abstract: According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.
    Type: Application
    Filed: February 22, 2018
    Publication date: March 21, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Satoshi KAMIYA
  • Patent number: 10194125
    Abstract: A projector apparatus includes a projection unit and a controller. The projection unit projects projection video of an image at a set angle of view on a projection surface in accordance with a video signal indicating the angle of view of the image including an object. The controller performs video signal processing for changing a position or size of the object in the image and controls the position or size of the projection video on the projection surface. In a case where the position or size of the object is to be changed by the video signal processing, when a resolution of the projection video of the changed object is less than a predetermined value, the controller controls the projection unit to decrease the angle of view so that the resolution of the projection video is equal to or greater than the predetermined value, and the controller sets the size of the object in the image by the video signal processing.
    Type: Grant
    Filed: June 18, 2016
    Date of Patent: January 29, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kunihiro Mima, Satoshi Kamiya, Keigo Ono
  • Patent number: D1007352
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: December 12, 2023
    Assignee: AZBIL CORPORATION
    Inventors: Raita Mori, Mayuka Sakai, Takayoshi Kawazu, Satoshi Kamiya, Mitsuhiko Nagata, Yasuhide Yoshikawa, Keisuke Obara