Abstract: Provided is a half bearing constituting a sliding bearing that is unlikely to cause damage during an operation of an internal combustion engine. The half bearing includes at least one protrusion, and the protrusion projects outward in a radial direction from an outer circumferential surface. A recessed portion that is recessed inward in the radial direction from the outer circumferential surface is formed over the entire inner-circumferential length between the protrusion and a circumferential-direction end surface of the half bearing. Two radial-direction grooves are formed in the circumferential-direction end surface of the half bearing relative to the protrusion, and each of the radial-direction grooves is adjacent to each of recessed portion side surfaces. The radial-direction grooves extend in the radial direction along the recessed portion side surfaces and are separated from the recessed portion at a midpoint of the extension.

Abstract: Provided is a half bearing constituting a sliding bearing that is unlikely to cause damage during an operation of an internal combustion engine. The half bearing includes at least one protrusion, and the protrusion projects outward in a radial direction from an outer circumferential surface. A recessed portion that is recessed inward in the radial direction from the outer circumferential surface is formed over the entire inner-circumferential length between the protrusion and a circumferential-direction end surface of the half bearing. Two radial-direction grooves are formed in the circumferential-direction end surface of the half bearing relative to the protrusion, and each of the radial-direction grooves is adjacent to each of recessed portion side surfaces. The radial-direction grooves extend in the radial direction along the recessed portion side surfaces and are separated from the recessed portion at a midpoint of the extension.

Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.

Abstract: A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.

Abstract: A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.

Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.

Abstract: According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.

Abstract: According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.

Abstract: An information processing apparatus comprises a central processor, a volatile memory, a non-volatile memory, a backup line, and a controller. The volatile memory is configured in such a manner that data is input and output thereto and therefrom via a bus under control of the central processor. The non-volatile memory is configured in such a manner that data is input and output thereto and therefrom via the bus under control of the central processor. The backup line is provided between the volatile memory and the non-volatile memory. The controller is configured to control data transfer performed between the volatile memory and the non-volatile memory via the backup line in a transition period between a normal mode of supplying normal power to the volatile memory and a low power consumption mode of reducing or interrupting normal power to be supplied to the volatile memory.

Abstract: A semiconductor device of an embodiment includes a path monitor circuit provided in a predetermined data path in a circuit that operates with a predetermined source clock, the path monitor circuit being configured to generate an output corresponding to a degree of a timing margin, a power supply voltage control circuit configured to set a power supply voltage that is used in the circuit based on an output of the path monitor circuit, and a clock generating circuit configured to supply to the circuit a clock obtained by dividing a frequency of the source clock, based on a detection result indicating that the power supply voltage obtained based on the output of the path monitor circuit becomes lower than a predetermined threshold.

Abstract: A semiconductor device of an embodiment includes a path monitor circuit provided in a predetermined data path in a circuit that operates with a predetermined source clock, the path monitor circuit being configured to generate an output corresponding to a degree of a timing margin, a power supply voltage control circuit configured to set a power supply voltage that is used in the circuit based on an output of the path monitor circuit, and a clock generating circuit configured to supply to the circuit a clock obtained by dividing a frequency of the source clock, based on a detection result indicating that the power supply voltage obtained based on the output of the path monitor circuit becomes lower than a predetermined threshold.

Abstract: According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.

Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.

Abstract: According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.

Abstract: According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.

Abstract: A projector apparatus includes a projection unit and a controller. The projection unit projects projection video of an image at a set angle of view on a projection surface in accordance with a video signal indicating the angle of view of the image including an object. The controller performs video signal processing for changing a position or size of the object in the image and controls the position or size of the projection video on the projection surface. In a case where the position or size of the object is to be changed by the video signal processing, when a resolution of the projection video of the changed object is less than a predetermined value, the controller controls the projection unit to decrease the angle of view so that the resolution of the projection video is equal to or greater than the predetermined value, and the controller sets the size of the object in the image by the video signal processing.

Abstract: An image forming device that includes a communication device includes a class judging unit, a number-of-times determination unit, and a retry execution unit. The communication device transmits data to a management device through a first communication network provided by a communication carrier. The class judging unit judges a class under which a first error having occurred in data transmission falls, the class being predetermined according to a probability of a successful transmission retry. The number-of-times determination unit determines the number of times a retry is performed in response to the first error, such that the number of times the retry is performed is decreased as the probability of a successful transmission retry becomes low. The retry execution unit causes the communication device to execute the retry in response to the first error the determined number of times.

Abstract: A user interface device for detecting an operation, by a finger of a user, on an operation member presented on a projection surface includes a distance detector for detecting a distance to the projection surface, and a distance to the finger, and a controller for detecting the operation based on the distances detected by the distance detector. When presence of the finger between the projection surface and the distance detector is determined, the controller calculates a normal vector of the projection surface based on distances from the distance detector to positions of at least three points on a surface of the projection surface and a distance from the distance detector to the finger, and detects, based on the normal vector, presence or absence of an operation on the operation member.

Abstract: A projector apparatus includes a projection unit and a controller. The projection unit projects projection video of an image at a set angle of view on a projection surface in accordance with a video signal indicating the angle of view of the image including an object. The controller performs video signal processing for changing a position or size of the object in the image and controls the position or size of the projection video on the projection surface. In a case where the position or size of the object is to be changed by the video signal processing, when a resolution of the projection video of the changed object is less than a predetermined value, the controller controls the projection unit to decrease the angle of view so that the resolution of the projection video is equal to or greater than the predetermined value, and the controller sets the size of the object in the image by the video signal processing.