Patents by Inventor Satoshi Kanegae

Satoshi Kanegae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11562837
    Abstract: Particularly, it is an object to provide a circuit substrate that can reduce a field intensity near an electrode having a high potential. A circuit substrate of the present invention includes an insulated substrate, a thin-film resistive element, and electrodes electrically connected to both sides of the thin-film resistive element, the thin-film resistive element and the electrodes being disposed on a surface of the insulated substrate. The circuit substrate is characterized in that the thin-film resistive element has a pattern in which a resistance wire is repeatedly folded back, and a dummy wire for reducing a field intensity is provided on a high-potential electrode side.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 24, 2023
    Assignee: KOA CORPORATION
    Inventor: Satoshi Kanegae
  • Publication number: 20220044849
    Abstract: Particularly, it is an object to provide a circuit substrate that can reduce a field intensity near an electrode having a high potential. A circuit substrate of the present invention includes an insulated substrate, a thin-film resistive element, and electrodes electrically connected to both sides of the thin-film resistive element, the thin-film resistive element and the electrodes being disposed on a surface of the insulated substrate. The circuit substrate is characterized in that the thin-film resistive element has a pattern in which a resistance wire is repeatedly folded back, and a dummy wire for reducing a field intensity is provided on a high-potential electrode side.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 10, 2022
    Applicant: KOA CORPORATION
    Inventor: Satoshi KANEGAE
  • Publication number: 20190198203
    Abstract: Provided is a surface-mountable thin film resistor network, which includes a chip, on which a thin film resistor network integrated array is formed, and a molded resin package, which encapsulate the chip. The surface-mountable thin film resistor network is provided with a chip (13) on which a thin film resistor integrated array has been formed; an island (12) on which the chip is fixed; a plurality of lead terminals (14) extending outward around periphery of the island; wires (15) connecting electrodes of resistors mounted on the chip to the lead terminals; and a molded resin package (20) that encapsulate a portion, which includes the wires; wherein a hanging lead (18) extending from the island is cut at an end surface of the molded resin package, and an electrical insulation (21) is applied to the cut section of the hanging lead.
    Type: Application
    Filed: June 2, 2017
    Publication date: June 27, 2019
    Applicant: KOA CORPORATION
    Inventors: Satoshi Kanegae, Tomonori Oguchi, Noboru Kashiwagi