Abstract: In a monitor circuit, bipolar-to-unipolar (B/U) converters are respectively connected to spare channels to convert bipolar test signals of pseudo-random sequence received therethrough to RZ (return-to-zero) signals and thereafter to NRZ signals. Each B/U converter includes a clock recovery circuit recover clock pulses from the RZ signal. The original pseudo-random sequence is recovered from successive instants of the NRZ signal of each B/U converter in response to successive clock pulses. Divide-by-M counters are respectively connected to the clock recovery circuits to generate low frequency clock pulses, which drive D flip-flops to convert the bit pattern of each pseudo-random sequence so that the edges of the binary digits in the converted sequence has a sufficient timing margin with respect to a sampling point at which mismatch is detected between the sequences derived from the space channels.

Abstract: In a phase-locked loop, a phase comparator, a low-pass filter, and a voltage-controlled oscillator are connected in a loop form. The phase-locked loop includes a switching circuit, arranged between the low-pass filter and the voltage-controlled oscillator, for switching an output signal from the phase comparator or an output signal from the low-pass filter to input the selected output signal to the voltage-controlled oscillator, and an input/output signal monitor circuit for controlling a switching timing of the switching circuit in response to a synchronization state between an input signal to the phase comparator and an output signal from the voltage-controlled oscillator, and in accordance with frequency components of the input signal.

Abstract: A protection channel monitoring system for monitoring a protection channel in a digital communication network comprises a transmitter (31) transmitting a check signal converted and split into a plurality of AMI code signals through the protection channel. The check signal is formed from a pseudo random signal provided by a pseudo random signal generator (15) driven by a pulse signal having a 1/N (N being an integer larger than 1) frequency of a clock pulse signal. The check signal comprises two predetermined N-bit code patterns each comprising logical "0" and "1" level bits. A receiver (32) receives the split AMI code signals through the protection channel and decode the AMI code signals to the NRZ code signals by sampling technique using a sampling signal being derived from one of the received AMI code signals and having the 1/N frequency of the clock pulse signal. Condition of the protection channel is decided by comparison of the decoded NRZ code signals.