Abstract: Disclosed is an antenna diversity receiver comprising an antenna switching control unit that includes a noise extraction unit that extracts noise from an FM detection output, a comparator that detects multipath interference from the extracted noise, a switching signal generation unit that outputs, to an antenna switching unit, an antenna switching signal directing switching from one antenna presently in use to another antenna, when multipath interference is detected, a modulation factor detection unit that obtains a modulation factor from the FM detection output, an over-modulation decision unit that decides whether or not the modulation factor is for over-modulation, and a sensitivity setting unit that, when it is decided that there is over-modulation, changes a multipath detection threshold for detecting multipath interference in the comparator, and performs setting to decrease sensitivity of detection of the multipath interference.

Abstract: The present invention provides an ATM cell assembling/disassembling apparatus capable of reducing power consumption. A reception VC detector 16 decides whether a reception cell is valid. A reception controller 17 performs disassembling and error check of a cell which has been decided to be valid by the reception VC detector 16 before issuing a DMA transfer request. A DMA output block 12 reads out a reception payload data from a reception data buffer 18 and DMA-transfers the data to a host memory 3. A reception clock controller 20 starts clock supply to the reception controller 17 when the reception VC detector 16 has decided that the reception cell is valid, and terminates the clock supply to the reception controller 17 upon completion of processing for one cell in the reception controller 17.

Abstract: A complex vector operation processor for carrying out a complex vector operation includes first and second multiplier sections, first to third adder sections, and a data output section. The first and second multiplier sections are provided in parallel. The first adder section is operatively connected with outputs of the first and second multiplier sections. The second and third adder sections are operatively connected with output of the first adder section and arranged in parallel. The data output section is operatively connected with the second and third adder sections to produce complex operation resultant data.

Abstract: In an ATM communication apparatus, when a transmission schedule section determines a transmission virtual channel, payload data corresponding to a plurality of cells is read out from a host memory if no payload for the virtual channel is present in a transmission payload temporarily storing section. The payload corresponding to a first cell, a corresponding cell header, and a corresponding cell trailer are formed into a transmission cell. The cell is transmitted to a physical layer device. Payloads corresponding to the second and subsequent cells are temporarily stored in the transmission payload temporarily storing section. When the transmission schedule section determines the virtual channel as a transmission virtual channel afterward, a payload is read out from the transmission payload temporarily storing section if the payload is stored therein. The read payload, corresponding header information, and corresponding trailer information are formed into a transmission cell.