Abstract: Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.

Abstract: Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.

Abstract: The present invention aims to provide an optical layered body that has excellent interlayer adhesiveness, particularly even in outdoor use, and also has highly excellent anti-blocking properties. The present invention relates to an optical layered body including: a substrate film; a hard coat layer containing silica fine particles on at least one surface of the substrate film; and a dry film layer on a surface of the hard coat layer opposite to the substrate film side surface of the hard coat layer, wherein the silica fine particles are exposed on the dry film layer side surface of the hard coat layer; the dry film layer is directly formed on the surface of the hard coat layer on which the silica fine particles are exposed; the hard coat layer before the formation of the dry film layer has projections and depressions on the surface on which the dry film layer is to be formed; the hard coat layer has an average silica fine particle abundance in ten 0.2 ?m×0.

Abstract: The present invention aims to provide an optical layered body that has excellent interlayer adhesiveness, particularly even in outdoor use, and also has highly excellent anti-blocking properties. The present invention relates to an optical layered body including: a substrate film; a hard coat layer containing silica fine particles on at least one surface of the substrate film; and a dry film layer on a surface of the hard coat layer opposite to the substrate film side surface of the hard coat layer, wherein the silica fine particles are exposed on the dry film layer side surface of the hard coat layer; the dry film layer is directly formed on the surface of the hard coat layer on which the silica fine particles are exposed; the hard coat layer before the formation of the dry film layer has projections and depressions on the surface on which the dry film layer is to be formed; the hard coat layer has an average silica fine particle abundance in ten 0.2 ?m×0.

Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.

Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.

Abstract: A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.

Abstract: Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.

Abstract: Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (3P1, 3P2; 3N1, 3N2). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (3I).

Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

Abstract: Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.

Abstract: Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (3I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (3P1, 3P2; 3N1, 3N2). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (3I).

Abstract: In a power MOSFET, on an N+ drain layer 21 as a substrate, a second N base layer 3 and a first N? base layer 22 are deposited in the order by epitaxial growth. In a surface portion of the layer 22, there are selectively formed a P base region 23, in a surface portion of which an N+ source region 24 is selectively formed. On a channel region in the P base region 23, a gate electrode 26 is formed with a gate insulator film 25 held between. A source electrode 27 and a drain electrode 28 are formed on the N+ source region 24 and on the back of the substrate, respectively. The layer 3 is made to have a thickness equal to or more than ¼ of that of the first N? base layer 22, and an averaged impurity concentration between 1×1015/cm3 and 3×1017/cm3. The thickness can be alternatively given as equal to or more than ½ of a difference between the thickness x shown as x(?m)=VSEB(V)/8 and that of the layer 22, where VSEB is an SEB(Single Event Burnout) voltage of the layer 3.

Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

Abstract: In a power MOSFET, on an N+ drain layer 21 as a substrate, a second N base layer 3 and a first N− base layer 22 are deposited in the order by epitaxial growth. In a surface portion of the layer 22, there are selectively formed a P base region 23, in a surface portion of which an N+ source region 24 is selectively formed. On a channel region in the P base region 23, a gate electrode 26 is formed with a gate insulator film 25 held between. A source electrode 27 and a drain electrode 28 are formed on the N+ source region 24 and on the back of the substrate, respectively. The layer 3 is made to have a thickness equal to or more than ¼ of that of the first N− base layer 22, and an averaged impurity concentration between 1×1015/cm3 and 3×1017/cm3.