Patents by Inventor Satoshi Kura

Satoshi Kura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936675
    Abstract: An estimation device (10) receives a device ID for identifying a device in a network and an observation event that has occurred in the device from a user terminal (20) as an input. The estimation device (10) acquires attribute information of the device corresponding to the received device ID from a device information storage unit (13c), estimates a risk that the device in the network is subject to an attack on the basis of the acquired attribute information and the received observation event, and outputs the estimated attack risk to the user terminal (20).
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 19, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Junko Hashimoto, Tsuneko Kura, Satoshi Takahashi, Megumi Uesu, Koji Kishi
  • Patent number: 10354996
    Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Kura, Mitsuo Nissa, Keiji Sakamoto, Taichi Iwasaki
  • Publication number: 20180158816
    Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.
    Type: Application
    Filed: January 30, 2018
    Publication date: June 7, 2018
    Inventors: Satoshi KURA, Mitsuo NISSA, Keiji SAKAMOTO, Taichi IWASAKI
  • Patent number: 9917083
    Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Kura, Mitsuo Nissa, Keiji Sakamoto, Taichi Iwasaki
  • Patent number: 8748282
    Abstract: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Kubota, Nobutaka Nagai, Satoshi Kura
  • Publication number: 20130277749
    Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.
    Type: Application
    Filed: April 8, 2013
    Publication date: October 24, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Satoshi Kura, Mitsuo Nissa, Keiji Sakamoto, Taichi Iwasaki
  • Patent number: 8410215
    Abstract: A thermoplastic resin composition contains (i) a polylactic acid, (ii) a polyolefin, and (iii) a compatibilizer (functional group-containing polymer that includes a functional group selected from functional groups X including a carboxyl group, an acid anhydride group, an epoxy group, a (meth)acryloyl group, an amino group, an alkoxysilyl group, a hydroxyl group, an isocyanate group, and an oxazoline group). The thermoplastic resin composition contains (iii-1) a functional group-containing hydrogenated diene polymer and (iii-2) a functional group-containing olefin polymer as the component (iii).
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: April 2, 2013
    Assignee: JSR Corporation
    Inventors: Takuya Sano, Toshiyuki Hayakawa, Takeo Nakamura, Teruo Aoyama, Akihiko Okubo, Satoshi Kura
  • Patent number: 8309414
    Abstract: A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toru Kawasaki, Satoshi Kura, Mitsuo Nissa, Naotaka Kamishita
  • Patent number: 8178641
    Abstract: A method for producing an amino group-containing conjugated diene polymer includes polymerizing a conjugated diene compound in the presence of a reaction product of 1,3-bis(diphenylethenyl)benzene or a derivative thereof and an organolithium compound to obtain a conjugated diene polymer, and reacting the conjugated diene polymer with a modifier.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: May 15, 2012
    Assignee: JSR Corporation
    Inventors: Satoshi Kura, Toshiyuki Hayakawa, Kazuhiro Iso, Susumu Komiyama
  • Publication number: 20110256686
    Abstract: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.
    Type: Application
    Filed: June 27, 2011
    Publication date: October 20, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo KUBOTA, Nobutaka NAGAI, Satoshi KURA
  • Patent number: 7985997
    Abstract: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: July 26, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Kubota, Nobutaka Nagai, Satoshi Kura
  • Publication number: 20110042749
    Abstract: A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.
    Type: Application
    Filed: July 22, 2010
    Publication date: February 24, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Toru Kawasaki, Satoshi Kura, Mitsuo Nissa, Naotaka Kamishita
  • Publication number: 20100267918
    Abstract: A method for producing an amino group-containing conjugated diene polymer includes polymerizing a conjugated diene compound in the presence of a reaction product of 1,3-bis(diphenylethenyl)benzene or a derivative thereof and an organolithium compound to obtain a conjugated diene polymer, and reacting the conjugated diene polymer with a modifier.
    Type: Application
    Filed: October 1, 2008
    Publication date: October 21, 2010
    Applicant: JSR CORPORATION
    Inventors: Satoshi Kura, Toshiyuki Hayakawa, Kazuhiro Iso, Susumu Komiyama
  • Publication number: 20090264591
    Abstract: A thermoplastic resin composition contains (i) a polylactic acid, (ii) a polyolefin, and (iii) a compatibilizer (functional group-containing polymer that includes a functional group selected from functional groups X including a carboxyl group, an acid anhydride group, an epoxy group, a (meth)acryloyl group, an amino group, an alkoxysilyl group, a hydroxyl group, an isocyanate group, and an oxazoline group). The thermoplastic resin composition contains (iii-1) a functional group-containing hydrogenated diene polymer and (iii-2) a functional group-containing olefin polymer as the component (iii).
    Type: Application
    Filed: August 23, 2007
    Publication date: October 22, 2009
    Applicant: JSR CORPORATION
    Inventors: Takuya Sano, Toshiyuki Hayakawa, Takeo Nakamura, Teruo Aoyama, Akihiko Okubo, Satoshi Kura
  • Publication number: 20080296729
    Abstract: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 4, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Ryo KUBOTA, Nobutaka Nagai, Satoshi Kura