Abstract: The present disclosure provides a power factor improvement circuit with a DC/DC converter including an arithmetic circuit. A first voltage having a full-wave rectified waveform is received by an input voltage detection terminal of the power factor improvement circuit. A second voltage is generated by amplifying an error between a first detection voltage and a reference voltage according to an output voltage of the DC/DC converter. A third voltage is generated by multiplying the first voltage by the second voltage. The arithmetic circuit adds an offset voltage to a third voltage to generate a fourth voltage. A comparator is configured to compare a second detection voltage with the fourth voltage. A drive circuit is configured to turn on/off drive of the switching transistor according to an output of the comparator. When the second detection voltage is higher than the fourth voltage, the switching transistor is turned off.

Abstract: A control circuit controls a power factor correction circuit including a DC-DC converter. The control circuit includes an amplifier configured to amplify a voltage commensurate with the output voltage of the DC-DC converter, a comparator configured to compare the output voltage of the amplifier with a slope voltage commensurate with the current passing through a switching element in the DC-DC converter, and a driver configured to drive the switching element based on the output voltage of the comparator. The control circuit is configured to adjust at least one of the gain of the amplifier and the gradient of the slope voltage in accordance with the load power of the DC-DC converter.

Abstract: The present disclosure provides a power factor improvement circuit with a DC/DC converter including an arithmetic circuit. A first voltage having a full-wave rectified waveform is received by an input voltage detection terminal of the power factor improvement circuit. A second voltage is generated by amplifying an error between a first detection voltage and a reference voltage according to an output voltage of the DC/DC converter. A third voltage is generated by multiplying the first voltage by the second voltage. The arithmetic circuit adds an offset voltage to a third voltage to generate a fourth voltage. A comparator is configured to compare a second detection voltage with the fourth voltage. A drive circuit is configured to turn on/off drive of the switching transistor according to an output of the comparator. When the second detection voltage is higher than the fourth voltage, the switching transistor is turned off.

Abstract: The present disclosure provides a power factor improvement circuit with a DC/DC converter including an arithmetic circuit. A first voltage having a full-wave rectified waveform is received by an input voltage detection terminal of the power factor improvement circuit. A second voltage is generated by amplifying an error between a first detection voltage and a reference voltage according to an output voltage of the DC/DC converter. A third voltage is generated by multiplying the first voltage by the second voltage. The arithmetic circuit adds an offset voltage to a third voltage to generate a fourth voltage. A comparator is configured to compare a second detection voltage with the fourth voltage. A drive circuit is configured to turn on/off drive of the switching transistor according to an output of the comparator. When the second detection voltage is higher than the fourth voltage, the switching transistor is turned off.

Abstract: The present disclosure provides a power factor improvement circuit with a DC/DC converter including an arithmetic circuit. A first voltage having a full-wave rectified waveform is received by an input voltage detection terminal of the power factor improvement circuit. A second voltage is generated by amplifying an error between a first detection voltage and a reference voltage according to an output voltage of the DC/DC converter. A third voltage is generated by multiplying the first voltage by the second voltage. The arithmetic circuit adds an offset voltage to a third voltage to generate a fourth voltage. A comparator is configured to compare a second detection voltage with the fourth voltage. A drive circuit is configured to turn on/off drive of the switching transistor according to an output of the comparator.

Abstract: A semiconductor device includes an external terminal, a switching output stage that performs switching drive of a terminal voltage at the external terminal, an output control unit arranged to generate a drive signal for the switching output stage according to an input pulse signal, a counter arranged to count the number of pulses of the input pulse signal so as to generate a mask signal, a logical gate arranged to mask the input pulse signal according to the mask signal, and a comparator arranged to compare the terminal voltage with a predetermined threshold value voltage so as to generate a reset signal of the counter.

Abstract: A controller IC has, for example, a current detection terminal for detecting a coil current passing in a switching power supply and an on-timing setter configured to check for a ground short circuit at the current detection terminal when an output transistor turns off to generate an on-timing setting signal so as to turn on the output transistor, during normal operation, at the time point that the coil current has decreased to a zero value or a value close thereto and, during a ground short circuit, after the lapse of a predetermined minimum off-period.

Abstract: A controller IC has, for example, a current detection terminal for detecting a coil current passing in a switching power supply and an on-timing setter configured to check for a ground short circuit at the current detection terminal when an output transistor turns off to generate an on-timing setting signal so as to turn on the output transistor, during normal operation, at the time point that the coil current has decreased to a zero value or a value close thereto and, during a ground short circuit, after the lapse of a predetermined minimum off-period.

Abstract: A semiconductor device includes an external terminal, a switching output stage that performs switching drive of a terminal voltage at the external terminal, an output control unit arranged to generate a drive signal for the switching output stage according to an input pulse signal, a counter arranged to count the number of pulses of the input pulse signal so as to generate a mask signal, a logical gate arranged to mask the input pulse signal according to the mask signal, and a comparator arranged to compare the terminal voltage with a predetermined threshold value voltage so as to generate a reset signal of the counter.

Abstract: In a touch-type input device, multiple sensor electrodes are arranged in a first coordinate axis direction. A capacitance detection circuit measures the electrostatic capacitances of the multiple sensor electrodes, and generates a first data array containing the capacitance value data which represents the electrostatic capacitances thus measured. A peak detection unit scans the first data array, identifies the sensor electrode which exhibits the largest capacitance, and generates first peak data which indicates the sensor electrode thus identified. Using the sensor electrode indicated by the first peak data as a reference, a computation processing unit reduces the value of the capacitance data of each sensor electrode arranged in a range within the capacitance value data contained in the first data array so as to generate a second data array, with the range having been selected using the sensor electrode indicated by the first peak data as a reference.