Patents by Inventor Satoshi Matagawa
Satoshi Matagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11456168Abstract: Provided is a method of lapping a semiconductor wafer, which can suppress the formation of a ring-shaped pattern in a nanotopography map. The method of lapping a semiconductor wafer includes: a stopping step of stopping lapping of a semiconductor wafer; a reversing step of reversing surfaces of the semiconductor wafer facing a upper plate and a lower plate after the stopping step; and a resuming step of resuming lapping of the semiconductor wafer after the reversing step while maintaining the reversal of the surfaces facing the plates.Type: GrantFiled: May 1, 2017Date of Patent: September 27, 2022Assignee: SUMCO CORPORATIONInventors: Daisuke Hashimoto, Satoshi Matagawa, Tomohiro Hashii
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Publication number: 20190252180Abstract: A wafer manufacturing method includes: a chamfering step of chamfering a wafer that is cut out from a monocrystal ingot and optionally lapped; a resin layer forming step of coating one surface of the chamfered wafer with a curable resin to form a resin layer, a first surface-grinding step of performing a surface grinding on the other surface of the chamfered wafer while holding the one surface through the resin layer; a resin layer removing step; and a second surface-grinding step of performing a surface grinding on the one surface while holding the other surface. Provided that a calculated average roughness of a chamfered portion of the chamfered wafer is represented by Ra (nm) and a viscosity of the curable resin to be applied is represented by V (mPa·s), the curable resin is applied in a manner satisfying a formula (1) below in the resin layer forming step.Type: ApplicationFiled: October 5, 2017Publication date: August 15, 2019Applicant: SUMCO CORPORATIONInventors: Toshiyuki TANAKA, Satoshi MATAGAWA
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Publication number: 20190181001Abstract: Provided is a method of lapping a semiconductor wafer, which can suppress the formation of a ring-shaped pattern in a nanotopography map. The method of lapping a semiconductor wafer includes: a stopping step of stopping lapping of a semiconductor wafer; a reversing step of reversing surfaces of the semiconductor wafer facing a upper plate and a lower plate after the stopping step; and a resuming step of resuming lapping of the semiconductor wafer after the reversing step while maintaining the reversal of the surfaces facing the plates.Type: ApplicationFiled: May 1, 2017Publication date: June 13, 2019Applicant: SUMCO CORPORATIONInventors: Daisuke HASHIMOTO, Satoshi MATAGAWA, Tomohiro HASHII
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Patent number: 8283252Abstract: A method of manufacturing a semiconductor wafer, including a step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by holding the semiconductor wafer in a wafer holding hole formed in a carrier plate, and simultaneously polishing a front and back surface of said semiconductor wafer by driving said carrier plate to make a circular motion associated with no rotation on its own axis within a plane parallel with a surface of said carrier plate between a pair of polishing members disposed to face to each other, by using an abrasive body with a semiconductor wafer sink rate different in polishing from that of an abrasive body for one of a polishing member on an upper surface plate and a polishing member on a lower surface plate so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer, or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.Type: GrantFiled: September 14, 2009Date of Patent: October 9, 2012Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida
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Publication number: 20100009605Abstract: A method of manufacturing a semiconductor wafer, including a step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by holding the semiconductor wafer in a wafer holding hole formed in a carrier plate, and simultaneously polishing a front and back surface of said semiconductor wafer by driving said carrier plate to make a circular motion associated with no rotation on its own axis within a plane parallel with a surface of said carrier plate between a pair of polishing members disposed to face to each other, by using an abrasive body with a semiconductor wafer sink rate different in polishing from that of an abrasive body for one of a polishing member on an upper surface plate and a polishing member on a lower surface plate so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer, or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.Type: ApplicationFiled: September 14, 2009Publication date: January 14, 2010Inventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida
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Patent number: 7589023Abstract: A method of manufacturing a semiconductor wafer, comprising the step of differentiating the glossiness of a front surface from that of a rear surface of the wafer by using an abrasive cloth with a semiconductor wafer sink rate different in polishing from that of the other abrasive cloth for one of a polishing cloth (14) on an upper surface plate (12) and a polishing cloth (15) on a lower surface plate (13) so as to simultaneously polish both the front and rear surfaces of the semiconductor wafer (W), or differentiating by differentiating the rotating speed of the upper surface plate from that of the lower surface plate.Type: GrantFiled: April 23, 2001Date of Patent: September 15, 2009Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida
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Publication number: 20090211167Abstract: A wire saw slurry containing, in a dispersing medium, 0.01-1 wt % of a metal film forming substance or a chelating agent that forms a film over copper in the dispersing medium. Entry of copper into a wafer bulk is prevented by the metal film forming substance or the chelating agent capturing the copper leaching out from brass plating of wires.Type: ApplicationFiled: February 19, 2009Publication date: August 27, 2009Applicant: SUMCO CORPORATIONInventors: Satoshi MATAGAWA, Akira NAKASHIMA, Takahisa NAKASHIMA, Kazushige TAKAISHI
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Publication number: 20030104698Abstract: An object of the present invention is to provide a semiconductor wafer having a front and a back surfaces polished so as to have different glossiness from each other, yet with a lower cost. The glossiness of the front surface and the back surface can be selected arbitrarily. In a double-sided polisher with no sun gear, silicon wafers W are inserted in respective holding holes 11a of a carrier plate 11. The wafers W are placed with their back surfaces facing up. An expanded urethane foam pad 14 is pressed against the back surfaces of the wafers W and a non-woven fabric pad 15 is pressed against the front surfaces of the wafers W. A carrier holder 20 and thus the carrier plate 11 are then driven to make a circular motion associated with no rotation on their own axes within a horizontal plane while supplying a slurry to the wafers W from an upper surface plate 12 side.Type: ApplicationFiled: October 23, 2002Publication date: June 5, 2003Inventors: Toru Taniguchi, Etsuro Morita, Satoshi Matagawa, Seiji Harada, Isoroku Ono, Mitsuhiro Endo, Fumihiko Yoshida