Patents by Inventor Satoshi Matsuyoshi
Satoshi Matsuyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8421232Abstract: A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material, and further including a method of producing the semiconductor device. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu6Sn5 content greater than a eutectic content.Type: GrantFiled: May 27, 2011Date of Patent: April 16, 2013Assignee: Hitachi, Ltd.Inventors: Osamu Ikeda, Masato Nakamura, Satoshi Matsuyoshi, Koji Sasaki, Shinji Hiramitsu
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Publication number: 20120212164Abstract: There is disclosed a semiconductor device capable of improving reliability, a rotating electrical machine using the semiconductor device or a vehicle using the semiconductor device. The semiconductor device includes Schottky barrier junctions and pn junctions. The pn junctions are provided in rectification areas and guard ring parts. Breakdown voltage at pn junctions in the rectification area is lower than breakdown voltage at the Schottky barrier junctions and the pn junctions in the guard ring parts.Type: ApplicationFiled: February 8, 2012Publication date: August 23, 2012Inventors: Takeshi TERAKAWA, Satoshi MATSUYOSHI, Kazutoyo NARITA, Mutsuhiro MORI
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Patent number: 8183681Abstract: A semiconductor device which includes a semiconductor chip; an electrically conductive base electrode bonded to the lower surface of the chip by a first bonding member; an electrically conductive lead electrode bonded to the upper surface of the chip by a second bonding member; and a first stress relief member for reducing stress developed in the first bonding member due to the difference in thermal expansion between the chip and the base electrode. Both the base electrode and the first stress relief member are in direct contact with the lower surface of the first bonding member. A protrusion is formed upstanding from the base electrode in direct contact with the first bonding member, and the first stress relief member surrounds a circumferential portion of the protrusion.Type: GrantFiled: June 29, 2009Date of Patent: May 22, 2012Assignee: Hitachi, Ltd.Inventors: Shinji Hiramitsu, Hiroyuki Ohta, Koji Sasaki, Masato Nakamura, Osamu Ikeda, Satoshi Matsuyoshi
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Publication number: 20110223718Abstract: A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material, and further including a method of producing the semiconductor device. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu6Sn5 content greater than a eutectic content.Type: ApplicationFiled: May 27, 2011Publication date: September 15, 2011Inventors: Osamu Ikeda, Masato Nakamura, Satoshi Matsuyoshi, Koji Sasaki, Shinji Hiramitsu
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Patent number: 7964492Abstract: A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material, and further including a method of producing the semiconductor device. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu6Sn5 content greater than a eutectic content.Type: GrantFiled: September 22, 2008Date of Patent: June 21, 2011Assignee: Hitachi, Ltd.Inventors: Osamu Ikeda, Masato Nakamura, Satoshi Matsuyoshi, Koji Sasaki, Shinji Hiramitsu
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Publication number: 20110042815Abstract: An object of the present invention is to provide, at low costs, an environmental friendly bonding material for a semiconductor, having sustained bonding reliability even when used at a temperature as high as 200° C. or higher for a long period of time, the semiconductor device having a semiconductor element, a supporting electrode body bonded to a first face of the semiconductor element via a first bonding member, and a lead electrode body bonded to a second face of the semiconductor element supported by the supporting electrode body via a second bonding member, the semiconductor device having a Ni-based plating layer and an intermetallic compound layer containing at least one of Cu6Sn5 and (Cu,Ni)6Sn5 compounds at an interface between the supporting electrode body and the first bonding member, and having a Ni-based plating layer and an intermetallic compound layer containing at least one of Cu6Sn5 and (Cu,Ni)6Sn5 compounds at an interface between the lead electrode body and the second bonding member.Type: ApplicationFiled: May 27, 2010Publication date: February 24, 2011Inventors: Osamu Ikeda, Satoshi Matsuyoshi
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Publication number: 20090321783Abstract: A semiconductor device which includes a semiconductor chip; an electrically conductive base electrode bonded to the lower surface of the semiconductor chip by a first bonding member; an electrically conductive lead electrode bonded to the upper surface of the semiconductor chip by a second bonding member; and a first stress relief member for reducing stress developed in the first bonding member due to the difference in thermal expansion between the semiconductor chip and the base electrode, wherein both the base electrode and the first stress relief member are in direct contact with the lower surface of the first bonding member.Type: ApplicationFiled: June 29, 2009Publication date: December 31, 2009Inventors: Shinji Hiramitsu, Hiroyuki Ohta, Koji Sasaki, Masato Nakamura, Osamu Ikeda, Satoshi Matsuyoshi
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Publication number: 20090159650Abstract: A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material, and further including a method of producing the semiconductor device. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu6Sn5 content greater than a eutectic content.Type: ApplicationFiled: September 22, 2008Publication date: June 25, 2009Inventors: Osamu Ikeda, Masato Nakamura, Satoshi Matsuyoshi, Koji Sasaki, Shinji Hiramitsu
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Patent number: 7423349Abstract: The present invention provides a semiconductor device comprising a semiconductor element and a copper member which are bonded to each other by a bismuth-based (Bi-based) bonding material having its melting temperature of not less than 250° C., wherein silver (Ag) is diffused in a region of the bonding material in the vicinity of an interface thereof to the semiconductor element with an inclination of concentration of the silver from the interface, in order to realize a manufacture of the semiconductor device without using lead (Pb) at low cost.Type: GrantFiled: April 27, 2006Date of Patent: September 9, 2008Assignee: Hitachi, Ltd.Inventors: Shosaku Ishihara, Osamu Ikeda, Ryouichi Kajiwara, Shinji Hiramitsu, Satoshi Matsuyoshi
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Publication number: 20070182023Abstract: By making coefficients of linear thermal expansion of stress relief members on upper and lower surface sides of a semiconductor chip small, thermal strain on joint members above and below the semiconductor chip is decreased and development of a crack therein is suppressed to ensure a joint area. Furthermore, by making areas of electrodes and stress relief members large enough to include a project plane of the semiconductor chip projected onto the joint surfaces thereof, even if a crack develops into the joint member between the stress relief member and the electrode, a joint area larger than the area of the semiconductor chip can be ensured for a certain amount of time. As a result, a semiconductor device capable of simultaneously ensuring the joint areas of the respective joint members and preventing a decrease in heat release capability is provided.Type: ApplicationFiled: January 16, 2007Publication date: August 9, 2007Applicant: Hitachi, Ltd.Inventors: Shinji Hiramitsu, Satoshi Matsuyoshi, Koji Sasaki, Takeshi Terasaki
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Patent number: 7193319Abstract: A semiconductor device is provided, in which buffer layers having a coefficient of linear expansion of 3×10?6/° C. to 8×10?6/° C. are joined to upper and lower surfaces of a silicon chip through a Pb-free solder having a thickness of not more than 0.05 mm and a melting point of not less than 250° C. The upper surface of the upper buffer layer and the lower surface of the lower buffer layer are respectively joined to a lead and a base through Pb-free solders having a thickness of not less than 0.15 mm and a melting point of not less than 250° C.Type: GrantFiled: November 29, 2005Date of Patent: March 20, 2007Assignee: Hitachi, Ltd.Inventors: Koji Sasaki, Shinji Hiramitsu, Tadaaki Kariya, Satoshi Matsuyoshi, Ryouichi Kajiwara, Shosaku Ishihara
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Publication number: 20070057021Abstract: A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material, and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu6Sn5 content greater than a eutectic content.Type: ApplicationFiled: June 21, 2006Publication date: March 15, 2007Inventors: Osamu Ikeda, Masato Nakamura, Satoshi Matsuyoshi, Koji Sasaki, Shinji Hiramitsu
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Publication number: 20060246304Abstract: The present invention provides a semiconductor device comprising a semiconductor element and a copper member which are bonded to each other by a bismuth-based (Bi-based) bonding material having its melting temperature of not less than 250° C., wherein silver (Ag) is diffused in a region of the bonding material in the vicinity of an interface thereof to the semiconductor element with an inclination of concentration of the silver from the interface, in order to realize a manufacture of the semiconductor device without using lead (Pb) at low cost.Type: ApplicationFiled: April 27, 2006Publication date: November 2, 2006Inventors: Shosaku Ishihara, Osamu Ikeda, Ryouichi Kajiwara, Shinji Hiramitsu, Satoshi Matsuyoshi
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Publication number: 20060214291Abstract: A semiconductor device is provided, in which buffer layers having a coefficient of linear expansion of 3×10?6/° C. to 8×10?6/° C. are joined to upper and lower surfaces of a silicon chip through a Pb-free solder having a thickness of not more than 0.05 mm and a melting point of not less than 250° C. The upper surface of the upper buffer layer and the lower surface of the lower buffer layer are respectively joined to a lead and a base through Pb-free solders having a thickness of not less than 0.15 mm and a melting point of not less than 250° C.Type: ApplicationFiled: November 29, 2005Publication date: September 28, 2006Inventors: Koji Sasaki, Shinji Hiramitsu, Tadaaki Kariya, Satoshi Matsuyoshi, Ryouichi Kajiwara, Shosaku Ishihara
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Patent number: 7002244Abstract: There is a need to provide a semiconductor device in which strain in a bonding member resulting from the difference in thermal deformation between a lead electrode and a semiconductor chip, which are electrically bonded to each other by the bonding member, is reduced for an improved thermal fatigue lifetime and the semiconductor chip has an improved current carrying capacity and enhanced heat dissipation.Type: GrantFiled: January 5, 2004Date of Patent: February 21, 2006Assignee: Hitachi, Ltd.Inventors: Misuk Yamazaki, Satoshi Matsuyoshi, Chikara Makajima
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Publication number: 20040135244Abstract: There is a need to provide a semiconductor device in which strain in a bonding member resulting from the difference in thermal deformation between a lead electrode and a semiconductor chip, which are electrically bonded to each other by the bonding member, is reduced for an improved thermal fatigue lifetime and the semiconductor chip has an improved current carrying capacity and enhanced heat dissipation.Type: ApplicationFiled: January 5, 2004Publication date: July 15, 2004Inventors: Misuk Yamazaki, Satoshi Matsuyoshi, Chikara Makajima
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Patent number: 5459338Abstract: A gate turn-off thyristor having a p-emitter layer in the anode side, an n-base layer, a p-base layer and an n-emitter layer in the cathode side. The n-base layer is composed of a first layer portion adjacent to the p-emitter layer, a second layer portion adjacent to the p-base layer and having a lower impurity concentration than the first layer portion, and is constituted by a structure which alters a travelling path of positive holes injected from the p-emitter layer.Type: GrantFiled: February 17, 1993Date of Patent: October 17, 1995Assignee: Hitachi, Ltd.Inventors: Yuji Takayanagi, Susumu Murakami, Yukimasa Satou, Satoshi Matsuyoshi, Yasuhiro Mochizuki, Hidekatsu Onose