Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: To perform execution scheduling of function blocks so as to control the total required power of the function blocks within a supplyable power budget value, and thereby realize stable operations at low power consumption. Function block identifiers are allotted to all the function blocks, and to a RAM area that a power consumption control device can read and write, a list to store identifiers and task priority, power mode value showing power states, and power mode time showing the holding time of power states can be linked. A single or plural link lists for controlling the schedules of tasks operating on the function blocks, a link list for controlling the function block in execution currently in high power mode, a link list for controlling the function block in stop currently in stop mode, and a link list for controlling the function block in execution currently in low power mode are allotted, and thereby the power source and the operation clock are controlled by the power consumption control device.

Abstract: A technology capable of efficiently performing the processes by using limited resources in an LSI where a plurality of real-time applications are parallelly processed is provided. To provide such a technology, a mechanism is provided in which a plurality of processes to be executed on a plurality of processing units in an LSI are managed throughout the LSI in a unified manner. For each process to be managed, a priority is calculated based on the state of progress of the process, and the execution of the process is controlled according to the priority. A resource management unit IRM or program that collects information such as a process state from each of the processing units executing the processes and calculates a priority for each process is provided. Also, a programmable interconnect unit and storage means for controlling a process execution sequence according to the priority are provided.

Abstract: A technology capable of efficiently performing the processes by using limited resources in an LSI where a plurality of real-time applications are parallelly processed is provided. To provide such a technology, a mechanism is provided in which a plurality of processes to be executed on a plurality of processing units in an LSI are managed throughout the LSI in a unified manner. For each process to be managed, a priority is calculated based on the state of progress of the process, and the execution of the process is controlled according to the priority. A resource management unit IRM or program that collects information such as a process state from each of the processing units executing the processes and calculates a priority for each process is provided. Also, a programmable interconnect unit and storage means for controlling a process execution sequence according to the priority are provided.

Abstract: A task control method by which when a multiprocessor device having processors executes application software tasks, checkpoints have been buried in the application software tasks in advance. In course of execution of each application software task, the checkpoints are used to make an inquiry about passed one of the checkpoints in the task. Then, the progress of each task is judged based on the current passed checkpoint identified as a result of the inquiry and a passed budget corresponding to the passed checkpoint. Based on a result of the judgment, a resource shared by the tasks is controlled, and a new passed budget is set. Thus, the restriction on the scope of application of an application software program is reduced.

Abstract: There is provided a semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device comprises: thermal sensors which can detect temperature, determine whether the detection result exceeds each of the above reference values and output the result; and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors, wherein the control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

Abstract: A chip (1) includes: a resource manager (2); various kinds of functional blocks (3-6); a thermal sensor (13); and a performance counter (15). The resource manager manages tasks that the functional blocks execute, and determines a task progress (38) for each task from an activated ratio (?) provided from the performance counter and a deadline (39) contained in task information (33) and decides priority of each task. When the temperature detected by the thermal sensor during execution of a task is not less than a threshold (T_max), the resource manager reads out a power consumption budget (P_max) from a memory (9) which has been set to make the temperature below the threshold, and stops the clock fed to the functional block executing a task having a lower priority or lowers the frequency of the clock until a chip power consumption value (p_sum) becomes smaller than the power consumption budget.

Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: To perform execution scheduling of function blocks so as to control the total required power of the function blocks within a supplyable power budget value, and thereby realize stable operations at low power consumption. Function block identifiers are allotted to all the function blocks, and to a RAM area that a power consumption control device can read and write, a list to store identifiers and task priority, power mode value showing power states, and power mode time showing the holding time of power states can be linked. A single or plural link lists for controlling the schedules of tasks operating on the function blocks, a link list for controlling the function block in execution currently in high power mode, a link list for controlling the function block in stop currently in stop mode, and a link list for controlling the function block in execution currently in low power mode are allotted, and thereby the power source and the operation clock are controlled by the power consumption control device.

Abstract: An information processing system that can reduce its power consumption by means of robust power controlling even upon occurrence of an interruption/exception processing. If it is found that there is no task set in the ready state as a result of watching the number of tasks set in the ready state by the RTOS or ready state watching task, the system controls the RTOS or ready state watching task so as to lower the power while the current active task controls the power according to the preset WCET of each application slice. On the contrary, if there is any task set in the ready state, the system controls so as to raise the power and the current active task comes to control the power according to the virtual WCET that is earlier than the WCET of each application slice. And, if there is no task set in the ready state and there is no current active task, the system controls so that the RTOS or both of the ready state watching task and sleep task lower the power.

Abstract: On the occasion of returning an error code to an application program to be executed under different execution environments of a computing system, it is requested to fully utilize a system of the existing instruction set to improve the ROM efficiency in the implementation of its common code and to eliminate useless insertion of instruction. For this purpose, in the present invention, a common error code to be returned, from the program to be used to be independent on different OS, to the execution program corresponding to the application program is determined as a value in the range of numerical value to be set with the instruction set of CPU and the defined instruction to load immediate value and thereby the common error code is held within the instruction code of the instruction to load immediate value. Particularly, a value of common error code is determined within the range where the MSB of the setting part of the instruction to load immediate value becomes zero (0).

Abstract: An information processing system that can reduce its power consumption by means of robust power controlling even upon occurrence of an interruption/exception processing. If it is found that there is no task set in the ready state as a result of watching the number of tasks set in the ready state by the RTOS or ready state watching task, the system controls the RTOS or ready state watching task so as to lower the power while the current active task controls the power according to the preset WCET of each application slice. On the contrary, if there is any task set in the ready state, the system controls so as to raise the power and the current active task comes to control the power according to the virtual WCET that is earlier than the WCET of each application slice. And, if there is no task set in the ready state and there is no current active task, the system controls so that the RTOS or both of the ready state watching task and sleep task lower the power.

Abstract: An information processing device which features low power consumption without deterioration in interruption request response speed. It specifies a waiting time until execution of a given event and makes a system call. It comprises: a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor capable of storing the waiting time upon the system call; and a first cycle supervisor capable of storing a time until the next interruption request from the first timer circuit. The timeout supervisor stores the time calculated by subtraction of the time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: On the occasion of returning an error code to an application program to be executed under different execution environments of a computing system, it is requested to fully utilize a system of the existing instruction set to improve the ROM efficiency in the implementation of its common code and to eliminate useless insertion of instruction.

Abstract: The invention provides a method for allocating registers for various execution environments. Various arguments are passed when a program for unifying various execution environments is called, then the parameters are stored in an argument information set part created in a memory's area pointed to by a general-purpose register. Accordingly, the number of registers actually used for storing the passed arguments is adjusted to be no greater than the number of registers reserved for storing the passed arguments. The number of passed arguments specified for a common function is also suppressed to be no greater than the number of registers for storing the passed arguments. The memory utilization efficiency is thus improved while the program execution speed is prevented from decreasing.