Abstract: An image-capturing apparatus, in which solid-state image-capturing elements having a large number of pixels are used, capable of suitably performing image-quality correction on a captured image. In a monitor reading mode, a camera system LSI (6) detects the read image signal which is read by thinning out pixels by an image-capturing device (3). Based on the detected data, control values for image-quality correction are computed in a microcomputer (9), and the camera system LSI (6) performs an image-quality correction process on the image signal based on these control values. When the image-capturing device shifts to a capture reading mode, the camera system LSI (6) temporarily stores the image signal, in which all the pixels are read, in the image memory (7), thereafter reads the image signal and detects it. The microcomputer (9) computes a control value on the basis of this detected data and the detected data in the previously used monitor reading mode.

Abstract: An image noise reduction method and apparatus to be used to digitize and process an image signal. Level values of peripheral pixels and the level value of a watched pixel are input into eight comparators and the value “1” is output when absolute values of differences between the level values are smaller than the value of a reference level. Signals output from the comparators are supplied to four AND circuits. The signals output from the AND circuits are supplied to eight AND gates in accordance with each combination and level values of corresponding peripheral pixels. Signals output from the AND circuits are supplied to an adder and the value “1” is added to the multiplication value and output to an output port-4. Thereby, the averaging operation is performed by using only pixels which solves the problem that an averaged signal phase is deviated from an original position.

Abstract: An image reduction method and apparatus to digitize and process an image signal. Level values a to h of peripheral pixels of a pattern, the level value of a watched pixel, and the value of a reference level ? are input. The level value o of the watched pixel is a gain set value ?, and added with the level values a to h output from the output ports of a selection circuit and supplied to a divider. The gain set value a is added with a value output from the selection circuit and supplied to the divider. The degree of signal processing is set by a ?-filter and the rate of watched pixels relating to the averaging operation is controlled and thereby, optionally setting the degree of signal processing.

Abstract: Picture quality degradation which occurs in a miniaturized image pick-up lens can be favorably corrected when image pick-up of a color picture is performed by providing an optical color filter on an image pickup surface of one piece of image pickup device. Through an image pick-up lens 1, image light is focused on an image pickup surface of an image pickup unit 2 for which a checkerboard shaped primary color filter is provided. An electrical signal taken out from the image pickup unit 2 is supplied to an A/D conversion circuit 3 to be converted into raw data of each primary color and is supplied to a first camera signal processing circuit 61 without any change. In the first camera signal processing circuit 61, only basic video signal processing such as, for example, gamma-correction or the like is performed. Then, the raw data of each primary color processed in the first camera signal processing circuit 61 is stored in a picture memory 4.

Abstract: An image-capturing apparatus, in which solid-state image-capturing elements having a large number of pixels are used, capable of suitably performing image-quality correction on a captured image. In a monitor reading mode, a camera system LSI (6) detects the read image signal which is read by thinning out pixels by an image-capturing device (3). Based on the detected data, control values for image-quality correction are computed in a microcomputer (9), and the camera system LSI (6) performs an image-quality correction process on the image signal based on these control values. When the image-capturing device shifts to a capture reading mode, the camera system LSI (6) temporarily stores the image signal, in which all the pixels are read, in the image memory (7), thereafter reads the image signal and detects it. The microcomputer (9) computes a control value on the basis of this detected data and the detected data in the previously used monitor reading mode.

Abstract: The present invention relates to an image noise reduction method and apparatus to be preferably used to digitize and process, for example, an image signal. Therefore, in the case of the present invention, level values a to h of peripheral pixels and the level value o of a watched pixel are respectively input to, for example, eight comparators 11 and the value “1” is output when absolute values of differences between the level values are smaller than the value of a reference level &thgr;. Moreover, peripheral pixels at point-symmetric positions about the watched pixel o are combined and signals output from the comparators 11 are supplied to four AND circuits 12 in accordance with combinations.

Abstract: The present invention relates to an image reduction method and apparatus to be preferably used to digitize and process, for example, an image signal. Therefore, in the case of the present invention, level values a to h of peripheral pixels of a pattern 1, the level value o of a watched pixel, and the value of a reference level &thgr; are input and level values a to h in which absolute values for differences between level values of peripheral pixels and the watched pixel are smaller than the value of the reference level &thgr; are output to output ports 3. Moreover, the value of the number of output ports 3 to which level values a to h is output to an output port 4. Moreover, the level value o of the watched pixel is supplied to a multiplier 9 and multiplied by an optional gain set value &agr;, and the multiplication value is supplied to an adder 5 and added with the level values a to h output from the output ports 3 of a selection circuit 2 and the addition value is supplied to a divider 7.