Abstract: A semiconductor device including a plurality of first diffusion layers that are formed over a semiconductor layer and disposed at predetermined intervals in a first direction, a plurality of second diffusion layers that are formed over the semiconductor layer, isolated from the first diffusion layers in a second direction orthogonal to the first direction, and disposed at the predetermined intervals in the first direction, a plurality of first regions that have a predetermined width in the first direction for separating the first diffusion layers from each other, a plurality of second regions that align with the first regions in the second direction and have the predetermined width for separating the second diffusion layers from each other, and a plurality of contacts that are formed over the first diffusion layers and over the second diffusion layers.

Abstract: A semiconductor memory device includes a sense amplifier section. The sense amplifier section includes first n-type diffusion layers, second n-type diffusion layers, first to fifth gates, and first to eighth contacts. The first to fourth contacts are formed over the first n-type diffusion layers. The fifth to eighth contacts are formed over the second n-type diffusion layers. The first and fourth gates are formed in a region between the first n-type diffusion layers. The third gate is formed in a region between the first n-type diffusion layers and in a region between the second n-type diffusion layers. The second and fifth gates are formed in a region between the second n-type diffusion layers.

Abstract: Disclosed is a semiconductor memory device that includes a sense amplifier section. The sense amplifier section includes first n-type diffusion layers, second n-type diffusion layers, first to fifth gates, and first to eighth contacts. The first to fourth contacts are formed over the first n-type diffusion layers. The fifth to eighth contacts are formed over the second n-type diffusion layers. The first and fourth gates are formed in a region between the first n-type diffusion layers. The third gate is formed in a region between the first n-type diffusion layers and in a region between the second n-type diffusion layers. The second and fifth gates are formed in a region between the second n-type diffusion layers.