Abstract: A travel sickness estimation system includes an estimation unit and an output unit. The estimation unit is configured to perform estimation processing of estimating, based on person information indicating conditions of a person who is on board a moving vehicle, whether or not the person is in circumstances that would cause travel sickness for him or her. The output unit is configured to output a result of the estimation processing performed by the estimation unit.

Abstract: Disclosed herein is an apparatus that includes a plurality of memory sections each including a plurality of word lines, a predecoder circuit configured to generate predecoded section address signals to select one of the plurality of memory sections and predecoded word line address signals to select one of the word lines included in a selected one of the plurality of memory sections based on a row address, and a section address control circuit configured to retain the predecoded section address signals regardless of an update of the row address in a test operation mode.

Abstract: Disclosed herein is an apparatus that includes a plurality of column planes each including a plurality of bit lines, an access control circuit configured to select one of the plurality of bit lines in each of the plurality of column planes based on a column address to read a plurality of data-bits, a data generating circuit configured to generate an expected-bit based at least in part on the data-bits, and an analyzing circuit configured to generate a fail-bit data indicating which one of the data-bits does not match the expected-bit when one of the data-bits does not match the expected-bit.

Abstract: Disclosed herein is an apparatus that includes a plurality of column planes each including a plurality of bit lines, an access control circuit configured to select one of the plurality of bit lines in each of the plurality of column planes based on a column address to read a plurality of data-bits, a data generating circuit configured to generate an expected-bit based at least in part on the data-bits, and an analyzing circuit configured to generate a fail-bit data indicating which one of the data-bits does not match the expected-bit when one of the data-bits does not match the expected-bit.

Abstract: Disclosed herein is an apparatus that includes a plurality of memory sections each including a plurality of word lines, a predecoder circuit configured to generate predecoded section address signals to select one of the plurality of memory sections and predecoded word line address signals to select one of the word lines included in a selected one of the plurality of memory sections based on a row address, and a section address control circuit configured to retain the predecoded section address signals regardless of an update of the row address in a test operation mode.

Abstract: A travel sickness estimation system includes an estimation unit and an output unit. The estimation unit is configured to perform estimation processing of estimating, based on person information indicating conditions of a person who is on board a moving vehicle, whether or not the person is in circumstances that would cause travel sickness for him or her. The output unit is configured to output a result of the estimation processing performed by the estimation unit.

Abstract: A storage unit includes a plurality of storage devices that form a RAID group, that are coupled to the same bus, and that communicate with each other. Each of the plurality of storage devices includes a device controller and a storage medium. The plurality of storage devices store each of data and parities generated on the basis of the data, the data and the parities being included in RAID stripes. A first device controller of a first storage device included in the RAID group transmits, to the plurality of storage devices included in the RAID group other than the first storage device, an instruction to transfer the data and/or the parities included in the RAID stripes and restores the data or the parity corresponding to the first storage device of the RAID stripes on the basis of the transferred data and the transferred parities.

Abstract: An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.

Abstract: The semiconductor memory device comprises a memory element group (one or more semiconductor memory elements) and a memory controller. The memory controller comprises a processor configured to process at least a part of an I/O command from a higher-level apparatus when the part of the I/O command satisfies a predetermined condition, and one or more hardware logic circuits configured to process the entire I/O command when the I/O command does not satisfy the predetermined condition.

Abstract: A purpose is to speed up a write process with a parity update. An information processing system includes storage devices constituting a RAID group, coupled to one bus and communicating with each other. Each of the storage devices includes a device controller and a storage medium for storing data. The storage devices include a first storage device storing old data and a second storage device storing old parity associated with the old data. A first device controller of the first storage device creates intermediate parity based on the old data and new data for updating the old data and transmit the intermediate parity to the second storage device specifying the second storage device storing the old parity associated with the old data, and a second device controller of the second storage device creates new parity based on the intermediate parity and the old parity.

Abstract: A semiconductor wafer is provided with a substrate, a GaN type semiconductor film which is laminated on the substrate, a plurality of element regions which are provided on the GaN type semiconductor film, a dielectric film which is laminated on the GaN type semiconductor film, and a dicing region which has a dicing groove which is provided in a lattice form without passing through the dielectric film described above so as to partition the element regions described above. Then, an end on the element region side of the dicing groove is higher or lower than a central portion of the dicing groove in a width direction in a bottom surface of the dicing groove.

Abstract: A storage unit includes a plurality of storage devices that form a RAID group, that are coupled to the same bus, and that communicate with each other. Each of the plurality of storage devices includes a device controller and a storage medium. The plurality of storage devices store each of data and parities generated on the basis of the data, the data and the parities being included in RAID stripes. A first device controller of a first storage device included in the RAID group transmits, to the plurality of storage devices included in the RAID group other than the first storage device, an instruction to transfer the data and/or the parities included in the RAID stripes and restores the data or the parity corresponding to the first storage device of the RAID stripes on the basis of the transferred data and the transferred parities.

Abstract: An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.

Abstract: A purpose is to speed up a write process with a parity update. An information processing system includes storage devices constituting a RAID group, coupled to one bus and communicating with each other. Each of the storage devices includes a device controller and a storage medium for storing data. The storage devices include a first storage device storing old data and a second storage device storing old parity associated with the old data. A first device controller of the first storage device creates intermediate parity based on the old data and new data for updating the old data and transmit the intermediate parity to the second storage device specifying the second storage device storing the old parity associated with the old data, and a second device controller of the second storage device creates new parity based on the intermediate parity and the old parity.

Abstract: The semiconductor memory device comprises a memory element group (one or more semiconductor memory elements) and a memory controller. The memory controller comprises a processor configured to process at least a part of an I/O command from a higher-level apparatus when the part of the I/O command satisfies a predetermined condition, and one or more hardware logic circuits configured to process the entire I/O command when the I/O command does not satisfy the predetermined condition.

Abstract: A semiconductor wafer is provided with a substrate, a GaN type semiconductor film which is laminated on the substrate, a plurality of element regions which are provided on the GaN type semiconductor film, a dielectric film which is laminated on the GaN type semiconductor film, and a dicing region which has a dicing groove which is provided in a lattice form without passing through the dielectric film described above so as to partition the element regions described above. Then, an end on the element region side of the dicing groove is higher or lower than a central portion of the dicing groove in a width direction in a bottom surface of the dicing groove.

Abstract: A data memory device has a command transfer direct memory access (DMA) engine configured to obtain a command that is generated by an external apparatus to give a data transfer instruction from a memory of the external apparatus; obtain specifics of the instruction; store the command in a command buffer; obtain a command number that identifies the command being processed; and activate a transfer list generating DMA engine by transmitting the command number depending on the specifics of the instruction of the command. The transfer list generating DMA engine is configured to: identify, based on the command stored in the command buffer, an address in the memory to be transferred between the external apparatus and the data memory device; and activate the data transfer DMA engine by transmitting the address to the data transfer DMA engine which then transfers the data to/from the memory based on the received address.

Abstract: This FET includes: a source electrode pad, which is formed on a source electrode and which is electrically connected to the source electrode; and/or a drain electrode pad, which is formed on the drain electrode and which is electrically connected to the drain electrode. The source electrode pad has a cutout for reducing a parasitic capacitance between the source electrode pad and the drain electrode, and the drain electrode pad has a cutout for reducing a parasitic capacitance between the drain electrode pad and the source electrode.

Abstract: A primary surface of a normally-off field-effect transistor (102) on which a source electrode (120) is formed and a first primary surface of a die pad (105) are in contact with each other, and the die pad (105) also serves as a source terminal of a semiconductor device (100). Accordingly, a semiconductor device capable of decreasing an inductance, which is a matter of great importance for an operation of a cascode connection circuit, and improving performance of circuit operation is provided.

Abstract: A nitride semiconductor device includes a substrate, a nitride semiconductor laminate, and an electrode metal layer. The electrode metal layer includes a first metal layer joined to the nitride semiconductor laminate and having a fine columnar structure including a plurality of columns, and a second metal layer disposed on the first metal layer and having a fine columnar structure including a plurality of columns. An average size of the columns of the fine columnar structure of the second metal layer in a column width direction is larger than an average size of the columns of the fine columnar structure of the first metal layer in a column width direction.