Patents by Inventor Satoshi Moriya

Satoshi Moriya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11945052
    Abstract: The present invention provides a brazing material application method that can stably discharge a brazing material containing a fluoride-based flux over a long period of time. The brazing material application method of the present invention includes: a supply step of supplying a liquid brazing material containing a fluoride-based flux to a liquid chamber of a discharge apparatus that is configured to have the liquid chamber having a discharge channel, a plunger disposed in the liquid chamber movably forward and backward, and a drive device for moving the plunger forward and backward and to satisfy a predetermined relationship; and an application step of discharging the brazing material in the liquid chamber from the discharge channel by moving the plunger toward the discharge channel of the liquid chamber by the drive device, and applying the brazing material to a metal member.
    Type: Grant
    Filed: December 25, 2020
    Date of Patent: April 2, 2024
    Assignee: HARIMA CHEMICALS, INC.
    Inventors: Aoi Tazuru, Satoshi Moriya, Daigo Kiga, Tomoaki Akazawa
  • Patent number: 11826859
    Abstract: A brazing material for brazing aluminum or an aluminum alloy includes fluoride-based flux, a solidifying agent, and a coating film uniformity agent, and is solid at 25° C.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: November 28, 2023
    Assignee: HARIMA CHEMICALS, INCORPORATED
    Inventors: Aoi Tazuru, Satoshi Moriya, Daigo Kiga
  • Publication number: 20230044980
    Abstract: The present invention provides a brazing material application method that can stably discharge a brazing material containing a fluoride-based flux over a long period of time. The brazing material application method of the present invention includes: a supply step of supplying a liquid brazing material containing a fluoride-based flux to a liquid chamber of a discharge apparatus that is configured to have the liquid chamber having a discharge channel, a plunger disposed in the liquid chamber movably forward and backward, and a drive device for moving the plunger forward and backward and to satisfy a predetermined relationship; and an application step of discharging the brazing material in the liquid chamber from the discharge channel by moving the plunger toward the discharge channel of the liquid chamber by the drive device, and applying the brazing material to a metal member.
    Type: Application
    Filed: December 25, 2020
    Publication date: February 9, 2023
    Applicant: HARIMA CHEMICALS, INC.
    Inventors: Aoi TAZURU, Satoshi MORIYA, Daigo KIGA, Tomoaki AKAZAWA
  • Publication number: 20220314378
    Abstract: A brazing material for brazing aluminum or an aluminum alloy includes fluoride-based flux, a solidifying agent, and a coating film uniformity agent, and is solid at 25° C.
    Type: Application
    Filed: August 13, 2020
    Publication date: October 6, 2022
    Applicant: Harima Chemicals, Incorporated
    Inventors: Aoi TAZURU, Satoshi MORIYA, Daigo KIGA
  • Publication number: 20220118540
    Abstract: In an application method of a solid brazing material, while being rotated, the solid brazing material is brought into contact with an aluminum plate material, thereby applying the solid brazing material to the aluminum plate material.
    Type: Application
    Filed: February 21, 2020
    Publication date: April 21, 2022
    Applicant: Harima Chemicals, Incorporated
    Inventors: Satoshi MORIYA, Aoi TAZURU, Daigo KIGA
  • Publication number: 20210187672
    Abstract: A brazing material for brazing aluminum or an aluminum alloy includes fluoride-based flux, a solidifying agent, and an organic viscosity reducing agent and is solid at 25° C.
    Type: Application
    Filed: August 20, 2019
    Publication date: June 24, 2021
    Applicant: Harima Chemicals, Incorporated
    Inventors: Wataru NOMURA, Daigo KIGA, Aoi TAZURU, Satoshi MORIYA
  • Patent number: 10576176
    Abstract: In a sterilizing system, a sterilizing device receives supply of oxygen and steam. The sterilizing device produces oxygen plasma containing ozone from the supplied oxygen and discharges the produced oxygen plasma and reactive oxygen produced through reaction between the supplied steam and the oxygen plasma as a sterilizing agent. And, the sterilizing system includes an ozone collecting unit for collecting ozone contained in the discharged oxygen plasma.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: March 3, 2020
    Assignee: SUNTORY HOLDINGS LIMITED
    Inventors: Kenichi Higashiyama, Kenta Tominaga, Yuji Hirayama, Kazuki Yoshihara, Toshiaki Iizuka, Satoshi Moriya
  • Publication number: 20180296715
    Abstract: In a sterilizing system, a sterilizing device receives supply of oxygen and steam. The sterilizing device produces oxygen plasma containing ozone from the supplied oxygen and discharges the produced oxygen plasma and reactive oxygen produced through reaction between the supplied steam and the oxygen plasma as a sterilizing agent. And, the sterilizing system includes an ozone collecting unit for collecting ozone contained in the discharged oxygen plasma.
    Type: Application
    Filed: October 12, 2016
    Publication date: October 18, 2018
    Applicant: SUNTORY HOLDINGS LIMITED
    Inventors: Kenichi HIGASHIYAMA, Kenta TOMINAGA, Yuji HIRAYAMA, Kazuki YOSHIHARA, Toshiaki IIZUKA, Satoshi MORIYA
  • Patent number: 8354730
    Abstract: A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS•FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: January 15, 2013
    Assignees: Hitachi, Ltd., Honda Motor Co., Ltd.
    Inventors: Satoshi Moriya, Toshio Saito, Goichi Yokoyama, Tsuyoshi Fujiwara, Hidenori Sato, Nobuaki Miyakawa
  • Patent number: 7948088
    Abstract: In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: May 24, 2011
    Assignees: Hitachi, Ltd., Honda Motor Co., Ltd.
    Inventors: Toshio Saito, Satoshi Moriya, Morio Nakamura, Goichi Yokoyama, Tatsuyuki Saito, Nobuaki Miyakawa
  • Publication number: 20100090307
    Abstract: A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS·FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.
    Type: Application
    Filed: August 25, 2006
    Publication date: April 15, 2010
    Inventors: Satoshi Moriya, Toshio Saito, Goichi Yokoyama, Tsuyoshi Fujiwara, Hidenori Sato, Nobuaki Miyakawa
  • Publication number: 20090174080
    Abstract: In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.
    Type: Application
    Filed: August 25, 2006
    Publication date: July 9, 2009
    Inventors: Toshio Saito, Satoshi Moriya, Morio Nakamura, Goichi Yokoyama, Tatsuyuki Saito, Nobuaki Miyakawa
  • Patent number: 7238296
    Abstract: When the entire amount of conductive metal mixed powder made of copper, manganese, and germanium is 100 parts by weight, the metal mixed powder is formed by mixing 4.0 to 13.0 parts manganese by weight, 0.2 to 1.4 parts germanium by weight, and 85.6 to 95.8 parts copper by weight, and 0 to 10 parts glass powder by weight and 0 to 10 parts copper-oxide powder by weight are mixed relative to the entire amount (100 parts by weight) of these metal components. The obtained resistive paste is then baked, and the resistive composition having the low resistance value and low TCR may be obtained. In addition, a resistor is made by forming the resistive element upon a substrate.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: July 3, 2007
    Assignee: KOA Kabushiki Kaisha
    Inventor: Satoshi Moriya
  • Publication number: 20060158304
    Abstract: A resistive material containing metallic powder including copper, manganese, and aluminum, glass powder and/ or copper oxide powder, and a vehicle is provided. The metallic powder is made by mixing 80 to 85 weight percent copper, 8 to 16 weight percent manganese, and 2 to 7 weight percent aluminum. A maximum of 10 weight percent glass powder and/ or copper oxide powder and 10 to 15 weight percent vehicle relative to the entire 100 weight percent metal mixed powder are added. The resulting resistive material is then wintered in an inactive atmosphere, thereby providing a resistor and a resistive element having target characteristics such as a low resistance, a low TCR value, and a low thermo-electromotive force.
    Type: Application
    Filed: December 15, 2003
    Publication date: July 20, 2006
    Inventor: Satoshi Moriya
  • Publication number: 20050230716
    Abstract: The object of the present invention is to suppress the increase of the contact resistance at the interface between the metal layer and the silicon plug in the wiring structure in which a metal layer is formed on and connected to a silicon plug. For its achievement, a lower semiconductor layer (drain) of a vertical-type MISFET is connected to an intermediate metal layer via an underlying plug composed of a polycrystalline silicon film, and a trap layer composed of a silicon nitride (TiN) film is formed on a part of the surface of the intermediate metal layer so as to surround the plug. The trap layer is formed in order to prevent an undesired high-resistance oxide layer from being formed at the interface between the plug and the intermediate metal layer.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 20, 2005
    Inventors: Satoshi Moriya, Toshiyuki Kikuchi, Akihiko Konno, Hidenori Sato, Naoki Yamamoto, Masamichi Matsuoka, Hiraku Chakihara, Akio Nishida
  • Publication number: 20040051085
    Abstract: When the entire amount of conductive metal mixed powder made of copper, manganese, and germanium is 100 parts by weight, the metal mixed powder is formed by mixing 4.0 to 13.0 parts manganese by weight, 0.2 to 1.4 parts germanium by weight, and 85.6 to 95.8 parts copper by weight, and 0 to 10 parts glass powder by weight and 0 to 10 parts copper-oxide powder by weight are mixed relative to the entire amount (100 parts by weight) of these metal components. The obtained resistive paste is then baked, and the resistive composition having the low resistance value and low TCR may be obtained. In addition, a resistor is made by forming the resistive element upon a substrate.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 18, 2004
    Inventor: Satoshi Moriya
  • Publication number: 20030216931
    Abstract: A contract between an IP provider and IP user is intermediated through examination of a semiconductor IP provided by the IP provider, registration of a semiconductor IP which has passed the examination and disclosure of the registered semiconductor IP, and evaluation of a system LSI realized on the basis of a semiconductor IP selected as a purchase candidate by the IP user from the disclosed semiconductor IPs.
    Type: Application
    Filed: October 28, 2002
    Publication date: November 20, 2003
    Inventors: Satoshi Moriya, Hisayoshi Kobayashi, Nobuyuki Miyazaki