Abstract: It is intended to provide a novel oligopeptide which can be relatively easily produced, has not only a hair growth-stimulating effect but also an effect of promoting the growth of epithelial cells (for example, skin regeneration) and can easily pass through the horny layer to thereby reach the desired target cells in which its effects are to be exerted. Namely, water-soluble oligopeptides containing a proryl isoleucyl glycyl unit or an isoleucyl glycyl serine unit and having from 3 to 7 amino acids and water-soluble salts thereof.

Abstract: A floating point divider includes a mantissa repetitive processing unit and an operation execution control unit. The mantissa repetitive processing unit calculates a quotient and a partial remainder by a digit-recurrence process for a mantissa of a dividend of an input operand. The operation execution control unit determines a bit value at a specified position uniquely specified based on a radix of an operation execution process with respect to the partial remainder. The mantissa repetitive processing unit reduces the number of digit-recurrence processes by calculating a quotient and a remainder based on a determining result of the operation execution control unit. The number of bits of the quotient is double of that of a quotient calculated once every the digit-recurrence process. The number of left-shift processes processed on the remainder is double of that of a remainder calculated once every the digit-recurrence process.

Abstract: In a semiconductor integrated circuit device in which dynamic type logic circuit cells, in which transistors constituting a logic section are in an unconnected condition, are arranged in two-dimensional array form and wiring for distributing a clock signal to each row of these dynamic type logic circuit cells is provided, a logic function is allotted to the cells, the number of series connection stages of the cells within an evaluation period determined by a clock cycle of the clock signal is found, and a judgment is made as to whether restrictions can be met by arranging the cells on the semiconductor integrated circuit device and performing delay calculations in a case where the number of series connection stages does not exceed a prescribed number of stages. When the restrictions are met, the whole processing comes to an end. When the restrictions are not met, modifications are made.

Abstract: It is intended to provide a novel oligopeptide which can be relatively easily produced, has not only a hair growth-stimulating effect but also an effect of promoting the growth of epithelial cells (for example, skin regeneration) and can easily pass through the horny layer to thereby reach the desired target cells in which its effects are to be exerted. Namely, water-soluble oligopeptides containing a proryl isoleucyl glycyl unit or an isoleucyl glycyl serine unit and having from 3 to 7 amino acids and water-soluble salts thereof.

Abstract: It is intended to provide a novel oligopeptide which can be relatively easily produced, has not only a hair growth-stimulating effect but also an effect of promoting the growth of epithelial cells (for example, skin regeneration) and can easily pass through the horny layer to thereby reach the desired target cells in which its effects are to be exerted. Namely, water-soluble oligopeptides containing a proryl isoleucyl glycyl unit or an isoleucyl glycyl serine unit and having from 3 to 7 amino acids and water-soluble salts thereof.

Abstract: A multiport cache memory is provided which enables reduction of a probability of bank contention which will occur when a plurality of read operations are executed simultaneously, and an access control system of the multiport cache memory.

Abstract: It is intended to provide a novel oligopeptide which can be relatively easily produced, has not only a hair growth-stimulating effect but also an effect of promoting the growth of epithelial cells (for example, skin regeneration) and can easily pass through the horny layer to thereby reach the desired target cells in which its effects are to be exerted. Namely, water-soluble oligopeptides containing a proryl isoleucyl glycyl unit or an isoleucyl glycyl serine unit and having from 3 to 7 amino acids and water-soluble salts thereof.

Abstract: In a semiconductor integrated circuit device in which dynamic type logic circuit cells, in which transistors constituting a logic section are in an unconnected condition, are arranged in two-dimensional array form and wiring for distributing a clock signal to each row of these dynamic type logic circuit cells is provided, a logic function is allotted to the cells, the number of series connection stages of the cells within an evaluation period determined by a clock cycle of the clock signal is found, and a judgment is made as to whether restrictions can be met by arranging the cells on the semiconductor integrated circuit device and performing delay calculations in a case where the number of series connection stages does not exceed a prescribed number of stages. When the restrictions are met, the whole processing comes to an end. When the restrictions are not met, modifications are made.

Abstract: The multiport cache memory in which cache block data registered in an address array and a data array as components of the cache memory is indexed by a plurality of access addresses to simultaneously execute processing of reading target data corresponding to each of the plurality of access addresses, with the address array and the data array being divided into a plurality of banks which can be unitarily identified by an index part lower-order bit of each access address.

Abstract: A shared memory type vector processing system in which CPUs are connected by a bus for transferring a vector processing instruction generated from any of the CPUs to each of the CPUs, and the respective CPUs are grouped into a master CPU which issues a vector processing instruction to other CPUs and slave CPUs operating as a multi-vector pipeline in synchronization with a vector processing unit in the master CPU, the master CPU including a memory access control unit for issuing said vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring said instruction to all the CPUs including its own CPU through a bus, and the master CPU and the slave CPU including a vector processing instruction control unit for comparing issuing source CPU information contained in a vector processing instruction and master CPU information set at its own CPU and conducting instruction issuance based on the vector processing instruction when the information accord

Abstract: A buffer is provided that has a high access time and operates with reduced power consumption. The buffer includes n write word line registers (40—0), each of which an output is directly connected to a word line driver. Thus, a word line is driven to access a memory cell array. All the word line registers are cascaded in a ring form. The write START signal 41 acting as a synchronous set input is input to the write word line register (40—0) corresponding to the least significant address. The write strobe (STB) signal 42 is input to the write word line registers connected in a ring form. When the write strobe signal 42 is active, the write word line registers operate like a shift register. When the write strobe signal 42 is not active, all the write word line registers hold a current value.

Abstract: A buffer is provided that has a high access time and operates with reduced power consumption. The buffer includes n write word line registers (40—0), each of which an output is directly connected to a word line driver. Thus, a word line is driven to access a memory cell array. All the word line registers are cascaded in a ring form. The write START signal 41 acting as a synchronous set input is input to the write word line register (40—0) corresponding to the least significant address. The write strobe (STB) signal 42 is input to the write word line registers connected in a ring form. When the write strobe signal 42 is active, the write word line registers operate like a shift register. When the write strobe signal 42 is not active, all the write word line registers hold a current value.