Patents by Inventor Satoshi NASUNO

Satoshi NASUNO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11776902
    Abstract: A semiconductor device includes a semiconductor substrate, a trench capacitor arranged on the semiconductor substrate, a first wiring layer, a second wiring layer, a first TSV penetrating the semiconductor substrate outside the trench capacitor, a second TSV penetrating the semiconductor substrate outside the trench capacitor, a first connecting terminal connected to the first TSV, a second connecting terminal connected to the first TSV, a third connecting terminal connected to the second TSV, and a fourth connecting terminal connected to the second TSV. A plurality of connecting terminals including the first through fourth connecting terminals are arranged dispersively over an entire area of the first wiring layer and the second wiring layer of the semiconductor device, thereby stabilizing voltage supplied to an image unit and achieving a stable image signal.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: October 3, 2023
    Assignee: Olympus Corporation
    Inventors: Katsumi Hosogai, Satoru Adachi, Takatoshi Igarashi, Satoshi Nasuno
  • Publication number: 20220028782
    Abstract: A semiconductor device includes a semiconductor substrate, a trench capacitor arranged on the semiconductor substrate, a first wiring layer, a second wiring layer, a first TSV penetrating the semiconductor substrate outside the trench capacitor, a second TSV penetrating the semiconductor substrate outside the trench capacitor, a first connecting terminal connected to the first TSV, a second connecting terminal connected to the first TSV, a third connecting terminal connected to the second TSV, and a fourth connecting terminal connected to the second TSV. A plurality of connecting terminals including the first through fourth connecting terminals are arranged dispersively over an entire area of the first wiring layer and the second wiring layer of the semiconductor device, thereby stabilizing voltage supplied to an image unit and achieving a stable image signal.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 27, 2022
    Applicant: OLYMPUS CORPORATION
    Inventors: Katsumi HOSOGAI, Satoru ADACHI, Takatoshi IGARASHI, Satoshi NASUNO